Wolfspeed, Inc.

Cree Gmbh

Shadi Sabri

Daniel Jenner Lichtenwalner

Edward Robert Van Brunt

Brett Hull

Brice McPherson

Thomas E Harrington, Iii

Joe W McPherson

Scott Thomas Allen

Roberto M Schupbach

Jianwen Shao

Matt N McCain

Prasanna Obala Bhuvanesh

Rahul R Potera

Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.

Semiconductor devices having on-chip gate resistors

Strategic placement and patterning of electrodes, vias, and metal runners can significantly reduce strain in a power semiconductor die. By modifying the path defining electrodes, vias, and metal runners, as well as patterning the material layers thereof, strain can be better managed to increase reliability of a power semiconductor die.

Power semiconductor device with reduced strain

A semiconductor device includes a semiconductor layer structure that includes silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. In some embodiments, a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer, and a lower surface of the gate electrode has recessed outer edges such as rounded and/or beveled outer edges.

Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices

Power semiconductor devices include multi-layer inter-metal dielectric patterns that include at least one reflowed dielectric material pattern and at least one non-reflowable dielectric material pattern. In other embodiments, power semiconductor devices include reflowed inter-metal dielectric patterns that are formed using sacrificial structures such as dams to limit the lateral spread of the reflowable dielectric material of the inter-metal dielectric pattern during the reflow process. The inter-metal dielectric patterns may have improved shapes and performance.

Power semiconductor devices having reflowed inter-metal dielectric layers

Semiconductor devices include a plurality of gate fingers extending on a wide bandgap semiconductor layer structure. An inter-metal dielectric pattern is formed on the gate fingers, the inter-metal dielectric pattern including a plurality of dielectric fingers that cover the respective gate fingers. A top-side metallization is provided on the inter-metal dielectric pattern and on exposed portions of the upper surface of the wide bandgap semiconductor layer structure. The top-side metallization includes a first conductive diffusion barrier layer on the inter-metal dielectric pattern and on the exposed portions of the upper surface of the wide bandgap semiconductor layer structure, a conductive contact layer on an upper surface of the first conductive diffusion barrier layer, and a grain stop layer buried within the conductive contact layer.

Power semiconductor devices having top-side metallization structures that include buried grain stop layers

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Cary, NC, United States of America

Shadi Sabri