Hewlett-packard Development Company, L.P.

Shad R Shepston

Jason Harold Culler

Karl Joseph Bois

Dacheng Zhou

David W Quint

Yong Wang

A system and method for providing compliant mapping between chip bond locations of an IC and corresponding package bond locations is disclosed. Package design information including package bond location information relating to the IC package and IC mask data including chip bond location information relating to the IC chip are integrated such that an internal physical design verification tool is operable to verify compliance between package bond locations and chip bond locations.

System and method for providing compliant mapping between chip bond locations and package bond locations for an integrated circuit

For a given channel and a filter having at least one filter tap, a set of at least one weight value is determined for the at least one filter tap according to which at least one weight value substantially minimizes a gradient of a frequency response for the given channel and substantially maximizes energy of the frequency response for the given channel within a predetermined bandwidth.

Determination of filter weights

An embodiment of this invention provides a circuit and method for reducing the number of electronic components needed to calibrate circuits on an IC. A multiplexer is located on the IC where the outputs of a plurality of circuits located on the IC are each connected to a separate data input of the multiplexer. The control input of the multiplexer selects which data input of the multiplexer is connected to an external component. Each data input is individually connected to the component periodically.

Growing community of inventors

Thornton, CO, United States of America

Shad R Shepston