Entropic Communications, Inc.

Conexant Systems, Inc.

Trident Microsystems (far East) Ltd.

Nxp B.v.

Shachar Kons

Zong Liang Wu

David Barr

Eran Arad

Shaw Yuan

Branislav A Petrovic

Michail Konstantinos Tsatsanis

Chi-ping Nee

Abraham Krieger

Gadi Kalit

Yoav GoldenBerg

Shimon Gur

Chun-Hsuan Kuo

Donald Brian Eidson

Efraim Dalumi

Ronen Hershkovitz

Uri Parker

Yoni Baron

An LDPC parity check matrix includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.

LDPC code matrices

An LDPC parity check matrix, includes a systematic portion having a plurality of systematic elements having a value, the value each systematic element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to that element; and a parity portion having a plurality of panty elements having a value, the value of each parity element determining a cyclic shift to be applied to rows of an identity submatrix corresponding to that element; wherein the weights of each column of a group of columns of the parity portion is the same. The LDPC parity check matrix may be used for data access, communication and storage, and may be used, for example for communications among a plurality of network nodes.

Systems and methods are provided for handling interference during communication of signals. A receive control signal may be generated in a transceiver leakage between a transmit path and a receive path in a transceiver, at least one signal applied or generated in the transmit path, and at least one signal applied or generated in the receive path. The receive control signal may then be applied adjust or control processing of received signals. One or more characteristics associated with the receive control signal may be set and/or adjusted based on one or more control signals applied to the transmit path. Transmit power may be tracked, and the receive control signal may be adjusted based on the tracking of the transmit power.

Transmit energy leakage control in a receiver

Systems and methods are provided for handling interference during communication of signals. A control signal based on leakage between the transmit path and the receive path, at least one signal applied in the transmit path during transmission of signals, and at least one signal generated in the receive path during processing of received signals. The control signal may then be applied into the receive path for use in completing processing of the received signals. One or more characteristics associated with the control signal may be set and/or adjusted based on one or more control signals applied in the transmit path. Characteristics of signals in the transmit path that may leak into the receive path may be tracked, and the control signal may be adjusted based on these Characteristics. Transmit power may be tracked, and the control signal may be adjusted based on the tracking of the transmit power.

An LDPC parity check matrix, includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of two or more columns of the parity portion are the same.

Systems and methods are provided for removing interference from received signals. An interference control signal may be generated in a transceiver during transmission and reception of signals. The interference control signal may be generated based on a first interference control input corresponding to an input signal used in generating the transmitted signals, and a second interference control input corresponding to a model of a leakage of the transmitted signals onto the received signals. The model may be based on a first approximation of a transfer function for the leakage. The interference control signal may be combined with an intermediate signal generated during processing of the received signals, to generate a corresponding combined signal, and the combined signal may be applied during processing of the received signals.

An LDPC parity check matrix includes a systematic portion having a plurality of systematic elements and a parity portion having a plurality of parity elements. The value of each systematic element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The value of each parity element determines a cyclic shift to be applied to rows of an identity submatrix corresponding to that element. The weights of each column of a group of columns of the parity portion are the same.

Systems and methods for removing interference from a received signal. A model of a leakage path from a transmit section to a receive section is used to assist in designing a set of iterative filters to remove interference. Modeling the leakage path allows generation of the first approximation of the transfer function of the leakage path traversed by the signals coupled from the transmit section to the receive section. The first approximation narrows down the universe of possible distortions that might occur due to the transfer function of the leakage path. Narrowing down the universe of possible solutions makes the complexity of the interference control section more manageable. An iterative LMS function is used to further refine the coefficients of the adaptive filters.

An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing. The decoder may also employ a novel method for generating check node to bit node messages through a prescribed series of pair-wise computations.

Efficient decoders for LDPC codes

A system for signal processing is provided. The system includes a steady state processing system for receiving a signal. A general purpose processing system is coupled to the steady state processing system and includes a signal acquisition system for receiving the signal and generating acquisition data. The steady state processing system can receive the acquisition data from the signal acquisition system and use the acquisition data to acquire the signal.

Signal acquisition system and method

An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Erasures assisted block code decoder and related method

A multi-channel decoder system has a decoder core at least a portion of which is configurable as a LDPC decoder that, during decoding processing, divides check nodes of a node representation of a LDPC code into a plurality of groups, and, during an iteration, sequentially processes the groups while processing in parallel the check nodes within each group, thus improving decoding throughput.

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Haifa, Israel

Shachar Kons