Yangtze Memory Technologies Co., Ltd.

Sha Sha Liu

Li Hong Xiao

Qian Tao

Yu Ting Zhou

Zhao Hui Tang

EnBo Wang

Zhenyu Lu

Yushi Hu

Xiaowang Dai

Zhaosong Li

Mei Lan Guo

Qianbing Xu

Qinxiang Wei

Jian Hua Sun

ZhiWu Tang

Haohao Yang

Sizhe Li

Enbo Wang

Feng Lu

Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.

Through array contact (TAC) for three-dimensional memory devices

Aspects of the disclosure provide a method for manufacturing a semiconductor device. A first structure of first stacked insulating layers including a first via over a contact region is formed. A second structure is formed by filling at least a top region of the first via with a sacrificial layer. A third structure including the second structure and second stacked insulating layers stacked above the second structure is formed. The third structure further includes a second via aligned with the first via and extending through the second stacked insulating layers. A fourth structure is formed by removing the sacrificial layer to form an extended via including the first via and the second via. A plurality of weights associated with the first structure, the second structure, the third structure, and the fourth structure is determined, and a quality of the extended via is determined based on the plurality of weights.

Methods of semiconductor device fabrication

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a first alternating conductor/dielectric stack disposed on the substrate and a layer of silicon carbide disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the silicon carbide layer. The memory device includes one or more first structures extending orthogonally with respect to the surface of the substrate through the first alternating conductor/dielectric stack and over the epitaxially-grown material disposed in the plurality of recesses, and one or more second structures extending orthogonally with respect to the surface of the substrate through the second alternating conductor/dielectric stack. The one or more second structures are substantially aligned over corresponding ones of the one or more first structures.

Memory device and forming method thereof

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Growing community of inventors

Hubei, China

Sha Sha Liu