International Business Machines Corporation

Globalfoundries Inc.

Seyoung Kim

Tayfun Gokmen

Choonghyun Lee

Soon-Cheon Seo

Injo Ok

Takashi Ando

Hiroyuki Miyazoe

Marwan H Khater

Paul Michael Solomon

Dennis Merton Newns

Kevin W Brew

Hyung-Min Lee

Mingu Kang

Effendi Leobandung

Talia S Gershon

Vijay Narayanan

Wilfried Haensch

Teodor Krassimirov Todorov

Yurii A Vlasov

Wooram Lee

Malte Johannes Rasch

Devendra K Sadana

Shu-Jen Han

Joel Pereira De Souza

Kyu-hyoun Kim

Yun Seog Lee

Chun-Chen Yeh

Oguzhan Murat Onen

Seonghoon Woo

Yulong Li

Kisup Chung

Asit Kumar Ray

Chih-Chao Yang

Stephen W Bedell

Ning Li

Jeehwan Kim

Oscar Van Der Straten

Cheng-Wei Cheng

Koichi Motoyama

Chia-Yu Chen

John Rozen

Zhibin Ren

Nanbo Gong

Glenn John Martyna

Mark B Ritter

Ko-Tao Lee

Joseph F Maniscalco

Jungwook Choi

Youngseok Kim

Wanki Kim

Marinus Hopstaken

Eun Kyung Lee

Pierce I-Jen Chuang

Hyungjun Kim

Kyu-Hyoun Kim

Jerry D Tersoff

Murat Onen

Mixed signal multipliers and methods for operating the same include a sampling capacitor and an accumulate capacitor. A sampling switch is configured to store an analog value on the sampling capacitor when a digital bit value of a digital signal is one and to store a zero when the digital bit value of the digital signal is a zero. An accumulate switch is configured to store an average of the stored value of the sampling capacitor and a previous stored value of the accumulate capacitor. A processor is configured to alternately trigger the sampling capacitor and the sampling capacitor for each bit value in the digital signal.

Dual capacitor mixed signal mutiplier

A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.

Area and power efficient implementation of resistive processing units using complementary metal oxide semiconductor technology

A processing unit, including a first circuit, and a first circuit element connected to the first circuit. The first circuit element is at least charged by the first circuit.

Circuit methodology for highly linear and symmetric resistive processing unit

A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.

Resistive memory device with magnetic layer having topological spin textures for tuning

A mixed-signal logic processor is provided. The mixed-signal logic processor includes a plurality of mixed-signal multiplier branches. Each of the plurality of mixed-signal multiplier branches has a set of branch-dedicated switches and a single branch-dedicated capacitor. The mixed-signal logic further includes a common switch. The common switch is external and common to each of the plurality of mixed-signal multiplier branches. The mixed-signal logic also includes a first shared branch-external capacitor and a second shared branch-external capacitor. The first and the second shared branch-external capacitors are external to and shared by each of the plurality of mixed-signal multiplier branches. Various settings of the set of switches and the common switch enable various modes of the mixed-signal dot product processor.

Mixed-signal dot product processor with single capacitor per multiplier

Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.

Resistive random-access memory device with step height difference

Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.

Dual damascene crossbar array for disabling a defective resistive switching device in the array

A neuromorphic device includes a plurality of first control lines, a plurality of second control lines and a matrix of resistive processing unit cells. Each resistive processing unit cell is electrically connected with one of the first control lines and one of the second control lines. A given resistive processing unit cell includes a first resistive device and a second resistive device. The first resistive device is a positively weighted resistive device and the second resistive device is a negatively weighted resistive device.

Formation failure resilient neuromorphic device

Provided are embodiments for a computer-implemented method, a system, and a computer program product for updating analog crossbar arrays. The embodiments include receiving a number used in matrix multiplication to represent using pulse generation for a crossbar array, and receiving a first bit-length to represent the number, wherein the bit-length is a modifiable bit length. The embodiments also include selecting pulse positions in a pulse sequence having the first bit length to represent the number, performing a computation using the selected pulse positions in the pulse sequence, and updating the crossbar array using the computation.

Sparse modifiable bit length deterministic pulse generation for updating analog crossbar arrays

An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.

Two-terminal non-volatile memory cell for decoupled read and write operations

A computer-implemented method for improving the efficiency of computing an activation function in a neural network system includes initializing, by a controller, weights in a weight vector associated with the neural network system. Further, the method includes receiving, by the controller, an input vector of input values for computing a dot product with the weight vector for the activation function, which determines an output value of a node in the neural network system. The method further includes predicting, by a rectifier linear unit (ReLU), which computes the activation function, that the output value of the node will be negative based on computing an intermediate value for computing the dot product, and based on a magnitude of the intermediate value exceeding a precomputed threshold value. Further, the method includes, in response to the prediction, terminating, by the ReLU, the computation of the dot product, and outputting a 0 as the output value.

Activation function computation for neural networks

A device configured to implement an artificial intelligence deep neural network includes a first matrix and a second matrix. The first matrix resistive processing unit ('RPU') array receives a first input vector along the rows of the first matrix RPU. A second matrix RPU array receives a second input vector along the rows of the second matrix RPU. A reference matrix RPU array receives an inverse of the first input vector along the rows of the reference matrix RPU and an inverse of the second input vector along the rows of the reference matrix RPU. A plurality of analog to digital converters are coupled to respective outputs of a plurality of summing junctions that receive respective column outputs of the first matrix RPU array, the second matrix RPU array, and the reference RPU array and provides a digital value of the output of the plurality of summing junctions.

Area and power efficient implementations of modified backpropagation algorithm for asymmetric RPU devices

Cross-point arrays and methods of updating values of the same include input resistive processing units (RPUs), each having a settable resistance, each connected to a common node. Output RPUs each have a settable resistance and are each connected to the common node. An update switch is configured to connect an update voltage to the common node.

Resistive crossbar arrays with reduced numbers of elements

Methods and systems for copying weight values between weight arrays includes reading outputs from a first array and reading outputs from a second array. Differences between respective outputs of the first array and the second array are determined. Values of the second array are adjusted in accordance with the determined differences.

Copying weights between resistive cross-point arrays

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White Plains, NY, United States of America

Seyoung Kim