Qualcomm Incorporated

Seyed Arash Mirhaj

Ankit Srivastava

Dinesh Jagannath Alladi

Lei Sun

Sameer Wadhwa

Elias Dagher

Yuhua Guo

Ganesh Kiran

Yan Wang

Ren Li

Chieh-Yu Hsieh

Masoud Ensafdaran

Anand Meruva

Aram Akhavan

Yongjian Tang

Zhongze Wang

Xiaonan Chen

Liang Dai

Guoqing Miao

Omid Rajaee

Kentaro Yamamoto

Balasubramanian Sivakumar

Suren Mohan

Changsok Han

Weihua Chen

Ji Ma

Xiaoke Wen

Seyfi Bazarjani

Certain aspects of the present disclosure provide techniques for performing machine learning computations in a compute in memory (CIM) array comprising a plurality of bit cells, including: determining that a sparsity of input data to a machine learning model exceeds an input data sparsity threshold; disabling one or more bit cells in the CIM array based on the sparsity of the input data prior to processing the input data; processing the input data with bit cells not disabled in the CIM array to generate an output value; applying a compensation to the output value based on the sparsity to generate a compensated output value; and outputting the compensated output value.

Sparsity-aware compute-in-memory

Various embodiments include devices and methods for a multi-bit multiplier-accumulator (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add a plurality of single-bit MAC outputs by receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs, and storing the plurality of single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs.

Analog adders for multi-bit MAC arrays in reconfigurable analog based neural networks

An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

Pipelined analog-to-digital conversion

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

Low-power compute-in-memory bitcell

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

Compute-in-memory bitcell with capacitively-coupled write operation

An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.

Analog-to-digital conversion

A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

Compute-in-memory with ternary activation

Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage to a reference voltage; and a calibration circuit coupled to the flash ADC and configured to tune the reference voltage prior to a conversion operation by the flash ADC.

Flash-successive approximation register (SAR) hybrid analog-to-digital converter (ADC)

A time-multiplexed group of MAC circuits for a machine learning application is provided in which at least one MAC circuit in the time-multiplexed group also functions as a capacitive-digital-to-analog converter (CDAC) within a successive approximation analog-to-digital converter (ADC). A comparator in the ADC is shared by the time-multiplexed group of MAC circuits.

Power-efficient compute-in-memory analog-to-digital converters

A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node.

Bootstrapped switch circuit with improved speed

Methods and apparatus for digitally controlling a common-mode voltage of a comparator. An example comparator circuit generally includes a first comparator and a sensing circuit configured to digitally track a common-mode voltage of the first comparator. The comparator circuit may further include a first capacitive array having a common terminal coupled to a first input of the first comparator and selectively coupled to an input of the sensing circuit. The comparator circuit may further include a second capacitive array having a common terminal coupled to a second input of the first comparator and selectively coupled to the input of the sensing circuit.

Digitally assisted control over comparator input common mode

Certain aspects of the present disclosure provide methods and apparatus for calibrating time-interleaved analog-to-digital converter (ADC) circuits and generating a suitable signal for such calibration. Certain aspects provide a signal generator for calibrating a time-interleaved ADC circuit having a plurality of channels. The signal generator generally includes a pattern generator configured to receive a periodic signal and to output a bitstream based on the periodic signal and a conversion circuit having an input coupled to an output of the pattern generator and configured to generate a waveform based on the bitstream. The bitstream has a bit pattern with a total number of bits that shares no common factor with a number of the channels and includes a relatively lower frequency component combined with a relatively higher frequency component.

Calibration for time-interleaved analog-to-digital converters and signal generators therefor

Multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits and methods for operating such receiver circuits are disclosed. One example receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.

Time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits for multi-channel receivers

Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Reducing signal dependence for CDAC reference voltage

Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

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San Diego, CA, United States of America

Seyed Arash Mirhaj