Advanced Micro Devices Corporation

Sey-Ping Sun

Mark I Gardner

David E Brown

Shengnian Davis Song

Hans Van Meer

Minh Van Ngo

Thomas E Spikes, Jr

Homi E Nariman

Bradley Marc Davis

H Jim Fulford

Fred N Hause

Robert Louis Dawson

Charles E May

Frederick N Hause

James N Pan

Darin A Chan

Hartmut Ruelke

Andrew Michael Waite

Robert Paiz

Terri Jo Kitson

John Caffall

Robert W Anderson

Kin-Sang Lam

Bradley Davis

A semiconductor product has different active thicknesses of silicon on a single semiconductor substrate. The thickness of the silicon layer is changed either by selectively adding silicon or subtracting silicon from an original layer of silicon. The different active thicknesses are suitable for use in different types of devices, such as diodes and transistors.

Semiconductor devices with active semiconductor height variation

A method far farming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors.

Method for forming semiconductor devices with active silicon height variation

A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.

Strain enhanced semiconductor devices and methods for their fabrication

A method for forming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors.

The carrier mobility in transistor channel regions of Si&#x2014;Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.

Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility

Carrier mobility in transistor channel regions is increased by depositing a conformal stressed liner. Embodiments include forming a silicon oxynitride layer on the stressed liner to reduce or eliminate deposition surface pattern sensitivity during gap filling, and in-situ SACVD of silicon oxide gap fill directly on the stressed liner with reduced pattern sensitivity. Embodiments also include the use of Si&#x2014;Ge substrates.

In-situ nitride/oxynitride processing with reduced deposition surface pattern sensitivity

A method of detecting silicide encroachment to the sidewalls of a gate electrode includes forming silicide at a device, with sidewall spacers defining a desired separation of the silicide from the sidewalls of the gate electrode. After silicide formation, the sidewall spacers are removed and line-of-sight monitoring is performed of the region previously obscured by the sidewall spacers, thereby permitting detection of silicide encroachment.

Method for detecting silicide encroachment of a gate electrode in a semiconductor arrangement

Various methods of inspecting a workpiece for residue are provided. In one aspect, a method of fabricating a conductor layer on a substrate is provided that includes forming an aluminum-copper film on the substrate in a first processing chamber and forming an anti-reflective coating on the aluminum-copper film in a second processing chamber. The substrate is moved from the second processing chamber into a cooling chamber to quench the substrate. A first time interval during which the substrate is in the first processing chamber and second time interval during which the substrate is present in the second processing chamber are measured. The substrate is annealed to restore a uniform equilibrium distribution of copper in the aluminum if the first time interval exceeds about 600 seconds or the second time interval exceeds about 300 seconds. The method substantially reduces the risk of metal comb bridging device failures following etch definition of conductor lines.

Method of fabricating conductor structures with metal comb bridging avoidance

A processing line includes a processing tool and an automatic process controller. The processing tool is adapted to deposit a layer of material on a semiconductor wafer based on an operating recipe. The automatic process controller is adapted to identify a post-idle set of wafers to be processed in the processing tool after an idle period, determine deposition times for wafers in the set of post-idle wafers, and modify the operating recipe of the processing tool for each of the wafers in the post-idle set based on the deposition times. A method for reducing wafer to wafer deposition variation includes designating a set of post-idle wafers; determining a deposition time for each of the wafers in the post-idle set, at least two of the deposition times being different; and depositing a layer on the wafers in the post-idle set based on the deposition times determined.

Method and apparatus for reducing wafer to wafer deposition variation

A device stack for fabrication of an isolation structure and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes exposing the substrate to a plasma ambient containing nitrogen and oxygen to form a nitrogen containing interface. An oxide film is formed on the nitrogen containing interface and a silicon rich nitride film is formed on the oxide film. The silicon rich nitride film is exposed to a plasma ambient containing oxygen to convert an upper portion of the silicon rich nitride film to silicon oxynitride. The optical properties of the nitride film are enhanced so that UV lithographic patterning of etch masking is improved.

In-situ stack for high volume production of isolation regions

The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.

Method of forming silicon oxynitride films

Methods of fabricating an isolation structure on a substrate are provided. In one aspect, a method of fabricating an isolation structure on a substrate is provided that includes forming a first insulating layer on the substrate wherein the first insulating layer has a first sidewall. A trench is formed in the substrate that has a second sidewall. A second insulating layer is formed in the trench. The second insulating layer displaces the second sidewall laterally. The first insulating layer is densified by heating to liberate gas therefrom and thereby move the first sidewall into substantial vertical alignment with the second sidewall. The risk of substrate attack due to trench isolation structure pullback is reduced. Trench edges are covered by thick isolation material.

Self-aligning silicon oxynitride stack for improved isolation structure

A method for fabricating an integrated circuit is presented. In the method, a dielectric layer is formed, and then a conductive layer is formed upon the dielectric layer. A base gate may then be patterned from the conductive layer. An intergate dielectric is preferably formed over and around the base gate. A spacer gate may then be formed such that at least a portion of the spacer gate is elevationally below an upper portion of the base gate. At least a portion of the intergate dielectric layer is preferably interposed between a sidewall surface of the spacer gate and a sidewall surface of the base gate. The final memory cell fabricated in this manner does not need to transfer electrons from a semiconducting substrate during operation.

Method for forming an integrated circuit memory cell and product thereof

A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N,O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N,O plasma is created by applying RF power to a showerhead from which the N,O is dispensed. By reacting an N,O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 &angst; and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N,O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N,O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N,O plasma versus the strong variation in oxide formation rates exhibited by thermal oxidation. Following gate oxide formation, a high temperature anneal may be performed, preferably in an RTA apparatus. By combining the N,O plasma treatment with an RTA process, the disclosed method is believed to offer a controllable and reproducible method for fabricating highly uniform, ultra-thin gate oxides, having low trapping state densities.

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Poughkeepsie, NY, United States of America

Sey-Ping Sun