Samsung Electronics Co., Ltd.

Seungyoung Lee

Sanghoon Baek

Taejoong Song

Jung-Ho Do

Jonghoon Jung

Jungho Do

Jinyoung Lim

Giyoung Yang

Jung Ho Do

Dongwoo Kim

Jinkyu Kim

Jeongho Kim

Wooyoung Choi

Jisu Yu

Myoung-ho Kang

Hyeongyu You

Seungman Lim

Mangun Hur

Hyeokseon Yu

Jaecheol Kim

Jaeho Park

Jongshik Ha

Heetae Oh

Jaewoong Han

Jaesoo Chaung

A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

Integrated circuit including standard cell and method of manufacturing the integrated circuit

Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

Stacked integrated circuit devices

A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

Semiconductor device

A semiconductor device includes: a device layer including first and second active patterns, extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction, intersecting the first direction, on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer, and including first and second lower wiring patterns extending in the first direction, located on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer, and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction. The first upper wiring pattern is connected to the first upper via without being connected to the second upper via and the second upper wiring pattern is connected to the second upper via without being connected to the first upper via.

Semiconductor device and manufacturing method of the same

An electronic device includes a system-on-chip (SoC) including at least one component, a memory, and a processor functionally connected to the SoC and the memory. The processor is configured to apply a default voltage for driving the at least one component at a specific frequency. The processor is also configured to determine whether data on an offset voltage corresponding to the at least one component and the specific frequency is stored. The processor is further configured to apply the offset voltage, being different from the default voltage, to the at least one component when the data on the offset voltage is stored. Other embodiments are possible.

Apparatus and method for applying suitable voltage to a component of a system-on-chip

A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

Semiconductor device including a gate electrode and a conductive structure

A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active patterns that extend in a second direction intersecting the first direction and that are spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active patterns, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active pattern of the first logic cell from the first active pattern of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.

Method of manufacturing semiconductor device

A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.

A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

Semiconductor device and method of fabricating the same

A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.

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Seoul, South Korea

Seungyoung Lee