International Business Machines Corporation

Samsung Electronics Co., Ltd.

Motorola Corporation

Advanced Micro Devices Corporation

Seungyoon P Song

Heonchul Park

Marvin A Denman

Le Trong Nguyen

Bryan P Black

Moataz A Mohamed

Mark A Kearney

Stephen C Horne

Gary Douglas Huber

Roney S Wong

Arturo Martin-de-Nicolas

David P Burgess

Ronald S Harter

Milton M Hood, Jr

Artie A Pennington

Graham R Murphy

Seongrai Cho

Lavanya Kling

Stephen P Horne

Jerry R Van Aken

Andrew R Raffman

In a multi-tasking computing system environment, one program is halted and context switched out so that a processor may context switch in a subsequent program for execution. Processor state information exists which reflects the state of the program being context switched out. Storage of this processor state information permits successful resumption of the context switched out program. When the context switched out program is subsequently context switched in, the stored processor information is loaded in preparation for successfully resuming the program at the point in which execution was previously halted. Although, large areas of memory can be allocated to processor state information storage, only a portion of this may need to be preserved across a context switch for successfully saving and resuming the context switched out program. Unnecessarily saving and loading all available processor state information can be noticeably inefficient particularly where relatively large amounts of processor state information exists. In one embodiment, a processor requests a co-processor to context switch out the currently executing program. At a predetermined appropriate point in the executing program, the co-processor responds by halting program execution and saving only the minimal amount of processor state information necessary for successful restoration of the program. The appropriate point is chosen by the application programmer at a location in the executing program that requires preserving a minimal portion of the processor information across a context switch. By saving only a minimal amount of processor information, processor time savings are accumulated across context save and restoration operations.

Efficient context saving and restoring in a multi-tasking computing

A processing system and method of operation are provided. A particular instruction is dispatched to execution circuitry for execution. After dispatching the particular instruction, an execution serialized instruction is dispatched to the execution circuitry prior to finishing execution of the particular instruction.

Method and system for reordering instructions after dispatch in a

A N-byte vector processor is provided which can emulate 2N-byte processor operations by executing two N-byte operations sequentially. By using N-byte architecture to process 2N-byte wide data, chip size and costs are reduced. One embodiment allows 64-byte operations to be implemented with a 32-byte vector processor by executing a 32-byte instruction on the first 32-bytes of data and then executing a 32-byte instruction on the second 32-bytes of data. Registers and instructions for 64-byte operation are emulated using two 32-byte registers and instructions, respectively, with some instructions requiring modification to accommodate 64-byte operations between adjacent elements, operations requiring specific element locations, operations shifting elements in and out of registers, and operations specifying addresses exceeding 32 bytes.

Scalable width vector processor architecture for efficient emulation

A wide data width processor has an execution unit including an aligner that aligns data for load/store instructions and shifts or rotates data for arithmetic logic instructions. Use of the same circuitry and execution unit for these different types of instructions reduces overall circuit size because alignment circuitry need not be repeated, once in a load/store unit and once in an arithmetic logic unit.

Multifunction data aligner in wide data width processor

A method for performing predictive translation of a data address in a computer processing system includes organizing a translation lookaside buffer in a set associative manner having each set associated with multiple entries, wherein the multiple entries store consecutively ordered selections. Further, the method includes selecting a set of entries in the translation lookaside buffer in response to a base operand for the predictive translation. The method also includes comparing each entry in the selected set with an input address for determining whether or not the predictive translation failed. The method further includes the step of adding the base operand with an offset operand to produce the effective address. A system in accordance with the present invention includes effective address generation logic, including a base operand register to hold a base operand, and a translation lookaside buffer, translation lookaside buffer. The translation lookaside buffer includes a multiple number of entries organized in a set associative manner to map a desired number of consecutive pages into a single set, and coupled to the effective address generation logic to utilize selected bits of the base operand for selection of a set of entries and for comparing each entry in the selected set with an input address for determining whether or not the predictive translation failed.

Predictive translation of a data address utilizing sets of associative

A superscalar processor includes an execution unit that executes load/store instructions and an execution unit that executes arithmetic instruction. Execution pipelines for both execution units include a decode stage, a read stage that identify and read source operands for the instructions and an execution stage or stages performed in the execution units. For store instructions, reading store data from a register file is deferred until the store data is required for transfer to a memory system. This allows the store instructions to be decoded simultaneously with earlier instructions that generate the store data. A simple antidependency interlock uses a list of the register numbers identifying registers holding store data for pending store instructions. These register number are compared to the register numbers of destination operands of instructions, and instructions having destination operands matching a source of store data are stalled in the read stage to prevent the instruction from destroying store data before an earlier store instruction is complete.

Deferred store data read with simple anti-dependency pipeline inter-lock

A vector processor includes two banks of vector registers where each vector register can stored multiple data elements and a control register with a field indicating a default bank. An instruction set for the vector processor includes instructions which use a register number to identify a vector registers in the default bank, uses a register number to identify a double-size vector register including a register from the first bank and a register from the second bank, and instructions which include a bank bit and a register number to access a vector register from either bank.

Single-instruction-multiple-data processing using multiple banks of

A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit predicts whether the condition precedent will be met the next time it encounters the same branch instruction. If the predicted value of the condition precedent would cause the branch to be taken, then the branch unit adds the fetch address-target address pair corresponding to the branch instruction to the BTAC. If the predicted value of the condition precedent would cause the branch to be not taken, then the branch unit deletes the fetch address-target address pair corresponding to the branch instruction from the BTAC.

Data processor with branch target address cache and method of operation

Instruction issue rate is enhanced by passing multiple instructions to a read stage when the number of required source operands exceeds the read capability of a register file but operand forwarding reduces the number of reads required. The multiple instructions can be issued for execution with source operands read from the register file and source operands forwarded from execution units without using maximum number of register file read ports in a superscalar vector processor architecture. Even when there is both inter-instruction data dependency and there are more source operands for, say, two instructions, to be fetched than available register file read ports, if some of the source operands can be obtained via result forwarding and the rest of the operands can be obtained via available register file read ports, the two instructions can be issued simultaneously. In an alternative embodiment, operand masking is implemented, which complicates the original scheme, as source operand mask and the mask of the result to be forwarded has to match.

Opportunistic operand forwarding to minimize register file read ports

A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the contents of the branch target address cache. If a hit occurs, then the data processor branches to the cached target address. The data processor also has a dispatch unit (60) that invalidates the data stored in the branch target address cache if and when it determines that the branch target address cache 'hit' on an instruction that was not a branch instruction at all, a 'phantom branch.' The data processor thereby automatically invalidates its branch target address cache data after a context switch.

Data processor with branch prediction and method of operation

The present invention provides a method and system for using hardware to assist software in emulating the guest instructions. The method and system comprises an emulation assist unit (EAU) which efficiently maps a guest instruction to a unique tag, an index, and an address of the corresponding semantic routine. The index determines where in a cache a plurality of tags are stored. A separate cache within the EAU stores each tag in association with the address the first time the corresponding guest instruction is emulated. Thus, the emulation assist unit also dynamically responds to the set of guest instructions being emulated. The first time a guest instruction is emulated, the EAU determines the address and stores the address in the cache in association with the tag. When the guest instruction is emulated again, the EAU uses the tag to access the stored addresses of the corresponding semantic routine.

Method and system for efficiently mapping guest instruction in an

The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the load/store unit writes back the data of each simple load instruction. This strategy facilitates early data forwarding for subsequent instructions. Conversely, the sequencer unit supplies a rename buffer tag to the load/store unit if it is not able to supply the operands of a simple store instruction.

Data processor with an execution unit for performing load instructions

A processing system and method of operation are provided. In response to multiple branch instructions, an instruction is processed prior to execution of the branch instructions. In response to execution of any of the branch instructions, the processing of the instruction is cancelled prior to completion of the executed branch instruction.

Processing system and method of operation for concurrent processing of

A processing system and method of operation are provided. Multiple instructions are dispatched in a sequence to execution circuitry. Ones of the instructions are executed with the execution circuitry, and respective results are output in response thereto, Each executed instruction is completed in response to finishing execution of each instruction preceding the executed instruction in the sequence, independent of whether the results are stored in at least one storage location specified by the completed instructions.

System for instruction completion independent of result write-back

A processing system and method of operation are provided. Multiple instructions are dispatched in a sequence to execution circuitry for execution. For each instruction, a determination is made in advance of execution about whether an exception is possible to result from execution of the instruction. An instruction is completed in response to determining an exception does not result from execution of the instruction and of each instruction preceding the instruction in the sequence, independent of whether the execution circuitry has finished execution of each instruction for which an exception is not possible.

Growing community of inventors

Austin, TX, United States of America

Seungyoon P Song