Stats Chippac Pte. Ltd.

SeungYong Chai

Yaojian Lin

Il Kwon Shim

Sungsoo Kim

Byung Joon Han

DeokKyung Yang

SungWon Cho

In Sang Yoon

KyoungHee Park

Hun Teak Lee

WonJun Ko

KyoWang Koo

Byung Tai Do

Jeffrey David Punzalan

KyungOe Kim

Bartholomew Liao Chung Foh

Dao Nguyen Phu Cuong

Kyung Moon Kim

Soo Won Lee

Kwok Keung Szeto

HunTeak Lee

Soyeon Park

OhHan Kim

Sang-Ho Lee

Jong Wook Ju

InSang Yoon

Taeg Ki Lim

JaEun Yun

Kenny Lee

GwangTae Kim

Ja Eun Yun

An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.

Integrated circuit packaging system with shielding and method of manufacture thereof

A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer. An insulating layer is deposited over the first conductive layer and second conductive layer. A third conductive layer includes a first portion of the third conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer. An electrical component is disposed over the first conductive layer and second conductive layer. An encapsulant is deposited over the first conductive layer, second conductive layer, and electrical component. A cut is made through the encapsulant, first conductive layer, and second conductive layer. A fourth conductive layer is deposited over side surfaces of the first conductive layer, second conductive layer, and encapsulant.

Dummy conductive structures for EMI shielding

An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.

Integrated circuit packaging system with substrate and method of manufacture thereof

Integrated circuit packaging system with shielding and method of manufacturing thereof

A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28&#xb0; C. to 260&#xb0; C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.

Semiconductor device and method of calibrating warpage testing system to accurately measure semiconductor package warpage

A semiconductor device has a build-up interconnect structure formed over an active surface of a semiconductor wafer containing a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the interconnect structure. Bumps are formed over the interconnect structure. A protective coating material is deposited over the insulating layer and saw street. A lamination tape is applied over the coating material. A portion of a back surface of the semiconductor wafer is removed. A mounting tape is applied over the back surface. The lamination tape is removed while leaving the coating material over the insulating layer and saw street. A first channel is formed through the saw street extending partially through the semiconductor wafer. The coating material is removed after forming the first channel. A second channel is formed through the saw street and the mounting tape is removed to singulate the semiconductor wafer.

Semiconductor device and method of forming protective coating material over semiconductor wafer to reduce lamination tape residue

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; depositing a through-conductor on the base substrate; depositing a semiconducting layer on the base substrate and around the through-conductor; forming a metal trace connected to the through-conductor; depositing a dielectric surrounding the metal trace; and removing the base substrate.

Integrated circuit packaging system with multi-stacked flip chips and method of manufacture thereof

An integrated circuit package system comprising: providing a base substrate; attaching a base integrated circuit die over the base substrate; forming a support over the base substrate near only one edge of the base substrate; and attaching a stack substrate over the support and the base integrated circuit die.

Integrated circuit package system with package integration

Growing community of inventors

Incheon, South Korea

SeungYong Chai