Samsung Electronics Co., Ltd.

Ybrain Inc.

Seungyeon Kim

Hongsoo Jeon

Daeseok Byeon

Pansuk Kwak

Kiwon Lee

Kyongsik Yun

Sunghoon Kim

Jin Yong Kim

Jong-Chul Choi

Sangwan Nam

Hyungwoo Lee

Jooyong Park

Kyung-Hwan Lee

Jiho Cho

Changbum Kim

Beakhyung Cho

Dongha Shin

Myeong-Woo Lee

Yoonjee Kim

You-Sub Shim

Takuya Futatsuyama

A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

Memory device including pass transistor circuit

A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.

Memory device having row decoder array architecture

A nonvolatile memory device includes a plurality of bit lines that is connected with a plurality of cell strings, a common source line that is connected with the plurality of cell strings, at least one dummy bit line that is provided between the common source line and the plurality of bit lines, a control logic circuit that generates at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver that selectively provides a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.

Nonvolatile memory device having a dummy bit line driver and operation method thereof

A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.

Memory device

A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.

3-dimensional memory device

The present disclosure relates to an electrical stimulation system, comprising, in accordance with one exemplary embodiment of the present invention, an analysis portion recognizing a brain activation pattern of a first user by analyzing a brainwave signal of the first user measured by a first electrical stimulation apparatus; and a stimulating portion applying an electrical stimulation to the brain of a second user on the basis of the information on the recognized brain activation pattern of the first user, wherein the first electrical stimulation apparatus includes a detecting portion detecting the second user's approach.

Electrical stimulation system

The present disclosure relates to an accounting method for electrical stimulation apparatus, comprising, in accordance with one exemplary embodiment of the present invention, receiving an information on authority for use of an electrical simulation apparatus from a second apparatus if a signal for payment request for the authority for use of the electrical simulation apparatus received from a first apparatus is processed and the information on the authority for use of the electrical stimulation apparatus is transmitted to a second apparatus; operating the electrical stimulation apparatus on the basis of the received information on the authority for use; collecting details of usage of the electrical stimulation apparatus; analyzing the collected details of usage; and renewing the received information on the authority for use on the basis of the analyzed details of usage.

Electrical stimulation system for recognizing brain activation pattern and applying electrical stimulation to a user

An electronic device includes a housing including a first plate, a second plate, and a side member a first band detachably mounted to the side member, and shaped to wrap around a wrist of a user; a display exposed through the first plate; a processor a memory and a mounting structure configured to connect the first band to the side member. The mounting structure includes a recessed structure formed in the side member, the recessed structure having a first surface, a second surface, a first hole formed in the first surface, and a second hole formed in the second surface, and facing the first hole, in which an imaginary line extending from the first hole to the second hole defines a first axis; a rotating member positioned to rotate around the first axis, the rotating member having a through-hole that has an inner screw surface centered around the first axis; a first rod extending along the first axis through a first portion of the first band, in which the first rod has a first end inserted into the first hole, and a second end held by the rotating member such that the first rod does not move along the first axis while the rotating member rotates; and a second rod extending along the first axis through a second portion of the first band. The second rod has: a third end rotatably inserted into the second hole; and an external screw surface engaged with the inner screw surface of the rotating member such that the second rod moves along the first axis while the rotating member rotates.

Growing community of inventors

Seoul, South Korea

Seungyeon Kim