Samsung Electronics Co., Ltd.

Hyundai Motor Company

Seoul National University

Korea Advanced Institute of Science and Technology

Seungwoo Seo

Seungwon Lee

Shinhaeng Kang

Yuhwan Ro

Hyunsoo Kim

Jaehyun Park

Sunjung Lee

Jungho Ahn

Jaewan Choi

Eojin Lee

Wonkyung Jung

Byeongho Kim

Minbok Wi

Jongwook Chung

Seongwook Park

Shin Hyoung Kim

Seongil O

Sung Il You

Ki Hong Kang

Jinwoo Shin

Hwayong Jang

Sungju Hwang

Hosang Yoon

Eunho Yang

Eunseog Cho

Haesik Jun

Jeong Sik Jin

Seongmin Park

Youyoung Song

Kyongmin Min

Jeongjae Park

Pilsung Koh

Jinseung Yoo

Mooseock Seo

A method of training a retrosynthesis prediction model includes determining first attention information from first character string information of a product, based on first graph information of the product, encoding the first character string information, based on the determined first attention information, and determining second attention information from the first graph information and second graph information of a reactant. The method further includes decoding second character string information of the reactant, based on the determined second attention information, and training the retrosynthesis prediction model, based on the decoded second character string information.

Method and apparatus for training retrosynthesis prediction model

A processor-in-memory (PIM) and a method of outputting an instruction using a PIM. The PIM includes an internal processor, a memory, and a register configured to store instruction meta information. The memory is configured to store a lookup table generated by predicting a future instruction. The external processor is configured to retrieve an instruction corresponding to the instruction meta information from the lookup table in response to a PIM application programming interface (API) call instruction including the instruction meta information. The instruction corresponding to the instruction meta information is output based on a retrieval result.

Processor-in-memory storing a lookup table for providing an instruction in response to an API call instruction

A memory device includes: memory operation circuitries to perform memory processing; memory banks assigned to one of the memory operation circuitries such that a set of n memory banks is assigned to each of the memory operation circuitries; and command pads to receive a command signal from an external source, wherein, for each of the memory operation circuitries, a corresponding memory operation circuitry to access memory banks of a corresponding set of n memory banks that is assigned to the corresponding memory operation circuitry, in an order determined based on respective distances from each of the memory banks of the corresponding set of n memory banks to the command pads, and wherein, each of the memory banks of the corresponding set of n memory banks to perform an access operation of data requested by the corresponding memory operation circuitry while the memory processing is performed.

Memory device for performing in-memory processing

A memory device configured to perform in-memory processing includes a plurality of in-memory arithmetic units each configured to perform in-memory processing of a pipelined arithmetic operation, and a plurality of memory banks allocated to the in-memory arithmetic units such that a set of n memory banks is allocated to each of the in-memory operation units, each memory bank configured to perform an access operation of data requested from the in-memory arithmetic units while the pipelined arithmetic operation is performed. Each of the in-memory arithmetic units is configured to operate at a first operating frequency that is less than or equal to a product of n and a second operating frequency of each of the memory banks.

A memory controller includes a first buffer configured to receive a first memory request from a host and store the first memory request, a request scheduler configured to determine an order in which the first memory request is transferred to a command generator, a request generator configured to generate one or more second memory requests based on a generation parameter of the first memory request, in response to an address of the first memory request corresponding to a processing in memory (PIM) memory, the command generator configured to generate a first command corresponding to the first memory request and one or more second commands corresponding to the one or more second memory requests, and store the generated first command and the one or more second commands in a second buffer, and a command scheduler configured to schedule the first command and the one or more second commands.

Memory controller and memory control method for generating commands based on a memory request

A memory controller, a method of operating the memory controller, and an electronic device including the memory controller are disclosed. The method of operating a memory controller, comprising receiving, from a host core, a plurality of commands for a memory, identifying, from among the plurality of commands, processing in memory (PIM) commands to execute one or more operations in the memory, verifying ordering information from a data field in each of the PIM commands, and reordering the PIM commands based on the ordering information and transmitting the reordered PIM commands to the memory.

Memory controller, method of operating the memory controller, and electronic device including the memory controller

A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Semiconductor memory device employing processing in memory (PIM) and operation method of the semiconductor memory device

A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.

A method of generating a 3D microstructure using a neural network includes configuring an initial 3D microstructure; obtaining a plurality of cross-sectional images by disassembling the initial 3D microstructure in at least one direction of the initial 3D microstructure; obtaining first output feature maps with respect to at least one layer that constitutes the neural network by inputting each of the cross-sectional images to the neural network; obtaining second output feature maps with respect to at least one layer by inputting a 2D original image to the neural network; generating a 3D gradient by applying a loss value to a back-propagation algorithm after calculating the loss value by comparing the first output feature maps with the second output feature maps; and generating a final 3D microstructure based on the 2D original image by reflecting the 3D gradient to the initial 3D microstructure.

Method and apparatus for reconstructing 3D microstructure using neural network

A removing poison apparatus of a lambda sensor includes: a lambda sensor detecting an oxygen concentration included in an exhaust gas; and a control unit differentiating a heating temperature and a heating time to remove poison of the lambda sensor depending on a lambda signal output from the lambda sensor in an overrun condition of the engine. By heating the lambda sensor depending on the magnitude of the lambda signal output from the lambda sensor, the lambda sensor may be inhibited from being degraded by combusting the material poisoned to the electrode of the lambda sensor and the failure of the lambda sensor may be correctly determined.

Apparatus and method for removing poison of lamda sensor

A method and device for a booting that can reduce a booting time is provided. The method includes loading a snapshot image from a non-volatile memory, setting an initialization of a device, decompressing the loaded snapshot image while the device is initialized, and loading another snapshot image from the non-volatile memory while decompressing the loaded snapshot image.

Apparatus and method for booting

A balance shaft module of an engine may include a balance weight shaped eccentrically in a radial direction from the axial center of a balance shaft, and a balance cover combined with the balance weight and defining a circumferentially-uniform outer surface with the balance weight with respect to the axial center of the balance shaft.

Balance shaft module of engine

Growing community of inventors

Seoul, South Korea

Seungwoo Seo