Agere Systems Inc.

Agere Systems Guardian Corp.

Lucent Technologies Inc.

Seungmoo Choi

Sailesh Mansinh Merchant

Pradip Kumar Roy

Donald Thomas Cwynar

Timothy Edward Doyle

Felix Llevada

Scott Francis Shive

Sailesh Chittipeddi

Alan Sangone Chen

William Thomas Cochran

Glenn B Alers

Stephen Arlon Meisner

Amal Ma Hamad

Vivek Saxena

Cheryl Anne Bollinger

Daniel Mark Wroge

Gerard Zaneski

Paul Yih

Troy A Giniecki

Pradip Kimar Roy

An integrated circuit device having a capacitor structure. In one form of the invention, an integrated circuit device includes a capacitor structure formed along a surface of a semiconductor layer. The capacitor structure includes a region formed in the semiconductor surface, a layer of dielectric material formed along a trench wall of the trench region and a first layer of doped polysilicon formed over the layer of dielectric material in the trench region. The capacitor structure further includes a second layer of doped polysilicon formed over the first layer of polysilicon.

Integrated circuit with a trench capacitor structure and method of manufacture

A method for manufacturing a semiconductor wafer uses a reticle having a plurality of spaced apart circuit images of identical patterns or images of a common level of a single integrated circuit formed on the reticle and arranged in columns and rows about its central point. At least one column of spaced apart test images are formed outside of and adjacent an outermost column of circuit images. Radiation is projected through the reticle for exposing the patterns on the reticle onto an underlying wafer. A reticle holder having a pair of shutter elements aligned parallel to the columns of images selectively blocks the projection of radiation through the columns of the test images but are exposed in order to form test circuits on the wafer at selected locations.

Multiple purpose reticle layout for selective printing of test circuits

To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.

Method of fabricating a silicon on insulator transistor structure for imbedded DRAM

A halo implant ( ) for an MOS transistor ( ) is formed in a semiconductor substrate ( ) at a shallow implant angle, relative to normal to the substrate surface ( ). A polysilicon gate structure ( ) is formed over a gate oxide ( ) and then a hard mask ( ), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface ( ) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask ( ). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

Method for fabricating MOS device with halo implanted region

An integrated circuit memory device includes a substrate having at least one connection line therein and a plurality of memory cells formed on the substrate. Each memory cell includes a pillar comprising a lower source/drain region for a cell access transistor electrically connected to the connection line, an upper source/drain region for the cell access transistor, and at least one channel region extending vertically between the lower and upper source/drain regions. Each memory cell further includes at least one lower dielectric layer vertically adjacent the substrate and laterally adjacent the pillar and at least one upper dielectric layer vertically spaced above the at least one lower dielectric layer and laterally adjacent the pillar. Further, each memory cell includes at least one gate for the at least one channel of the cell access transistor between the lower and upper dielectric layers so that the vertical spacing therebetween defines a gate length for the cell access transistor. A storage capacitor is also included in each memory cell adjacent the upper source/drain region of the cell access transistor and is electrically connected thereto.

Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method

The present invention provides a method of manufacturing a resistor for use in a memory element and a semiconductor device employing the resistor. The method of manufacturing may comprise forming a dielectric layer over an active region of a semiconductor wafer and forming a resistive layer on the dielectric layer. The resistive layer comprises a compound wherein a first element of the compound is a Group III or Group IV element and a second element of the compound is a Group IV or Group V element. The method further comprises connecting an electrical interconnect structure to the resistive layer that electrically connects the resistive layer to the active region.

High resistivity film for 4T SRAM

The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor wafer and first and second active areas are in contact with the tub. In one advantageous embodiment, the interconnect is formed in the tub and is in electrical contact with the first and second active areas. The interconnect extends from the first active area to the second active area to electrically connect the first and second active areas.

Device and method for forming semiconductor interconnections in an integrated circuit substrate

A semiconductor integrated circuit device and method of forming same is disclosed and includes a silicon substrate having a field oxide region and spaced active region. First and second self-aligned contact window openings are associated with a respective field oxide region and active region. A dummy polysilicon landing pad is formed over the field oxide region and formed below the first self-aligned contact window opening. An operative polysilicon landing pad is formed above the dummy landing pad. A silicon nitride barrier layer is also formed during the process.

Semiconductor device having self-aligned contact and landing pad structure and method of forming same

A contactless, self-aligned local interconnect structure provides a continuous silicide film electrically coupling an upper silicon structure to a lower silicon structure. The upper silicon structure overlaps the lower silicon structure and is insulated from the lower silicon structure by an insulating layer formed between the structures. The continuous silicide film electrically couples the two structures by bridging the gap formed by the insulating layer in the overlap region. The associated process for forming the local interconnect structure includes forming a lateral edge of the upper silicon structure extending over the lower silicon structure, forming a blanket metal film, then heating the metal film such that the metal film reacts with the exposed silicon of the upper silicon structure and the lower silicon structure to form a continuous silicide film which bridges the gap formed by the insulating layer which is formed of a thickness chosen to be suitably low. After the silicide film is formed, unreacted portions of the metal film are removed.

Contactless local interconnect process utilizing self-aligned silicide

An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor of the cell is formed in a first well in a dielectric layer overlying the cell transistor. The top electrode of the capacitor also serves as a barrier layer between an underlying plug in a second well in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.

Method for forming a DRAM capacitor having a high dielectric constant dielectric and capacitor made thereby

A diffusion barrier for preventing the diffusion of oxygen from a high dielectric constant material to a titanium nitride layer. The diffusion barrier comprises one or more layers, wherein each of the one or more layers comprises a material selected from the group consisting of metal carbide, metal nitride, metal boride, metal carbo-nitride, and silicon carbide. The high dielectric constant material may be tantalum pentoxide or any perkovskite-type high dielectric constant material.

Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same

An integrated circuit device includes a dielectric layer having an opening therein, and a capacitor comprising in stacked relation a lower electrode lining the opening, a capacitor dielectric layer adjacent the lower electrode, and an upper electrode adjacent the capacitor dielectric layer. The capacitor has a substantially planar upper surface substantially flush with adjacent upper surface portions of the dielectric layer. Additionally, the edges of the lower electrode and the capacitor dielectric layer preferably terminate at the upper surface of the capacitor. Also, the capacitor dielectric may include a high-k, high quality and low leakage dielectric, and which prevents the reduction of the capacitor dielectric by the metal of the upper and lower metal electrodes.

Integrated circuit device having dual damascene capacitor

A method for making a semiconductor device includes forming a plurality of transistors in a semiconductor substrate, forming a first dielectric layer overlying the semiconductor substrate, and selectively etching the first dielectric layer to form a first opening exposing a first transistor portion and a second transistor portion. Conducting material is deposited into the first opening to define a merged contact between the first transistor portion and the second transistor portion. The method further includes forming a second dielectric layer overlying the first dielectric layer and the merged contact, and selectively etching the second dielectric layer to form a second opening exposing the merged contact, and while selectively etching the second and first dielectric layers to form a third opening exposing a source/drain region of a third transistor to define a self-aligned contact. Conducting material is deposited into the second opening to define a first via with the merged contact, and conducting material is also deposited into the third opening to define a second via with the source/drain region of the third transistor. The self-aligned contact and the merged contact are formed using a reduced number of masks and masking steps.

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Orlando, FL, United States of America

Seungmoo Choi