Samsung Electronics Co., Ltd.

Seungman Lim

Minsu Kim

Sanghoon Baek

Ahreum Kim

Jisu Yu

Hyeongyu You

Seungyoung Lee

Jeongjin Lee

Jaewoo Seo

Hyunchul Hwang

Chunghee Kim

Hakchul Jung

Jaeho Park

A flip-flop (FF) includes a first n-channel metal oxide semiconductor (NMOS) transistor connected to a ground line, a first p-channel metal oxide semiconductor (PMOS) transistor connected to a power voltage line, a second NMOS transistor connecting a first node to the first NMOS transistor, a second PMOS transistor connecting the first node to the first PMOS transistor, a third NMOS transistor and a fourth NMOS transistor, connected to the second NMOS transistor in parallel, and forming a first discharge path for connecting the first node to the ground line, a third PMOS transistor and a fourth PMOS transistor, connected to the second PMOS transistor in parallel, and forming a first charge path for connecting the first node to the power voltage line, a keeper circuit connected to the first node to maintain a voltage level of the first node.

Flip-flop based on clock signal and pulse signal

An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

Integrated circuit and method of designing the same

A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

Integrated circuit including standard cell and method of manufacturing the integrated circuit

A multi-bit flip-flop includes a first flip-flop having a first output driver connected to a first output pin and arranged on a first row, a second flip-flop including a second output driver electrically connected to a second output pin and arranged on a second row, and an internal hold buffer connected to the first output driver on the first row and the second flip-flop on the second row.

Multi-bit flip-flop and integrated circuit including the same

An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.

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Siheung-si, South Korea

Seungman Lim