Samsung Electronics Co., Ltd.

Seungki Hong

Jongmin Bang

Geuntae Park

Seung-jun Lee

Minho Choi

Youngjae Park

Woongdai Kang

Wonil Bae

Jaeseong Lim

Minsoo Jang

Jinsol Park

Eunki Hong

Heonsu Jeong

A memory device includes plural banks that perform a per-bank refresh (PBR) operation, and an address register that provides a single row address signal to two banks of the plural banks, the two banks simultaneously performing the PBR operation and the single row address signal being shared by the two banks. The two banks activate a word line of each memory cell array based on a single decoded row address signal that is generated based on the single row address signal.

Memory device and operation method thereof

A method of operating a memory device includes precharging a pair of true and complementary bit lines (BL/BLB) to an equivalent voltage concurrently with precharging a pair of true and complementary sense bit lines (SABL/SABLB) to the equivalent voltage, and then transferring charge associated with offset noise from BL to SABLB concurrently with transferring charge associated with the offset noise from BLB to SABL, so that a voltage difference is established between the SABL and SABLB. Next, a logic state of a memory cell connected to BI is read by transferring charge between the memory cell and BL, concurrently with equilibrating voltages on SABL and SABLB. Then, a voltage difference between SABL and SABLB is sensed and amplified in response to activating an amplifier circuit within the sense amplifier.

Memory devices having sense amplifiers therein that support offset cancellation having improved sense amplifier characteristics and methods of operating same

A memory device and a method of precharging a decoded address are provided. The memory device includes a memory cell array including a plurality of rows; a row decoder configured to select a row to be activated from among the plurality of rows based on a decoded row address; and an interface circuit configured to: generate the decoded row address based on decoding a plurality of bits of a row address, transfer the decoded row address to the row decoder, and in an idle non-power-down mode of the memory device, precharge the decoded row address that is transferred to the row decoder in response to a predetermined condition being satisfied.

Memory device and precharging method thereof

A method of operating a semiconductor memory device includes setting an operating mode of a mode register to a first operating mode to allow a refresh operation to be performed at intervals of a first period, counting an active command and a pre-charge command by control logic in the first operating mode to generate counting information, comparing a threshold count value with the counting information by the control logic to determine whether the counting information reaches the threshold count value, generating an adaptive mode signal by the control logic when it is determined that the counting information reaches the threshold count value and setting the operating mode of the mode register to a second operating mode in which the refresh operation is performed at intervals of a second period in response to the adaptive mode signal. The second period is less than the first period.

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a command and address generator configured to decode a command to generate an active command, and generate an address applied with the active command as a row address, a control signal generator configured to generate sequence data changing with a random sequence in response to the active command, and generate a random pick signal when the sequence data is equal to previously stored comparison data, and a memory cell array comprising an odd page memory cell array including a plurality of first memory cells and an even page memory cell array including a plurality of second memory cells, and configured to simultaneously perform the active operation and a hidden hammer refresh operation on the selected first and second memory cells in response to the row address when the random pick signal is activated in response to the active command.

Semiconductor memory device and memory system having the same

A memory device and a method of precharging a decoded address are provided. The memory device includes a memory cell array comprising a plurality of rows; a row decoder configured to select a row to be activated from among the plurality of rows based on a decoded row address; and an interface circuit configured to: generate the decoded row address based on decoding a plurality of bits of a row address, transfer the decoded row address to the row decoder, in a first mode of the memory device, precharge the decoded row address that is transferred to the row decoder, and in a second mode of the memory device, determine whether a precharge signal is received in the second mode, and precharge the decoded row address based on the precharge signal.

An operating method of a memory device, the method including, receiving a row address, determining whether an operating mode is a byte mode, counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode, selecting a target row hammer address among target row addresses using access count values for the target row hammer address, calculating a victim row address corresponding to the target row hammer address, and performing a target refresh operation on the victim row address.

Memory device, a memory system having the same and an operating method thereof in which a row address is not separated depending on pages in a byte mode operation

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, a normal refresh row address generator, a hammer refresh row address generator, a refresh selection signal generator, and a selector. The normal and hammer refresh row address generators generates a normal refresh row address and a hammer refresh row address, respectively, in response to a refresh counting control signal. The refresh selection signal generator sequentially generates normal and hammer refresh selection signals in response to the refresh counting control signal. The selector selects the normal refresh row address or the hammer refresh row address in response to the normal and hammer refresh selection signals. A normal refresh operation and a hammer refresh operation are sequentially performed on a memory cell array block among plural memory cell array blocks in response to the refresh row address.

A memory device is provided. The memory device includes: a memory cell array including a plurality of rows; and a refresh control circuit including a plurality of registers each configured to store a row address. The refresh control circuit is configured to: determine, based on an incoming row address satisfying a replacement condition, in a first determination, whether to replace a first row address stored in a first register among the plurality of registers with the incoming row address based on a replacement probability; maintain the first row address stored in the first register or replace the first row address stored in the first register with the incoming row address based on a first result of the first determination; and determine, in a second determination, a victim row address to be refreshed based on a second row address stored in a second register among the plurality of registers.

Memory device and refresh method thereof

A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a fingerprint read signal generator configured to generate a fingerprint read signal in response to a refresh counting control signal, a memory cell array comprising a plurality of sub memory cell array blocks, a fingerprint output unit configured to receive data output from memory cells connected to one selected among a plurality of word lines and one selected among a plurality of bit lines of one among the plurality of sub memory cell array blocks in response to the fingerprint read signal to generate fingerprint data, and a pseudorandom number generator configured to perform a linear feedback shifting operation in response to an active command to generate sequence data, receive the fingerprint data in response to the fingerprint read signal, and generate the sequence data based on the fingerprint data.

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Incheon, South Korea

Seungki Hong