Samsung Electronics Co., Ltd.

Nanyang Technological University

Samsung Electro-mechanics Co., Ltd.

Seungjin Park

Junghwan Choi

Youngdon Choi

Youngchul Cho

Doobock Lee

Mingyu Lee

Baek Jin Lim

Seunghoon Lee

Myoungbo Kwak

Jueon Kim

Hojun Yoon

Jihwan Hyun

Taehyoung Kim

Kwangsub Byun

Taehwan Kim

Cheolwoo Park

Byungkwon Kang

Seokjae Lee

Sungjin Son

Baekjin Lim

Junil Kang

The disclosed multilayer ceramic capacitor may include: a ceramic main body; an internal electrode disposed inside the ceramic main body; and an external electrode including a plating layer that contacts a surface of the ceramic main body and is connected to the internal electrode, in which a micro crack exists inward from a surface of the ceramic main body where the plating layer is in contact, and the micro crack may be filled with a metal that comprises the plating layer, and the surface of the ceramic main body, which is in contact with the plating layer, may include an amorphous structure.

Multilayer ceramic capacitor

A semiconductor device includes a first power node configured to supply a first power supply voltage, a pull-up circuit electrically connected between the first power node and an output node that is configured to output a signal, and a controller configured to output a pull-up control code to the pull-up circuit. The pull-up circuit includes a plurality of unit circuits electrically connected to each other in parallel between the first power node and the output node, and the plurality of unit circuits include a first unit circuit and a second unit circuit. The number of current paths provided by the first unit circuit between the first power node and the output node is different from the number of current paths provided by the second unit circuit between the first power node and the output node.

Semiconductor device

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

Memory device and operating method of a memory device

A nonvolatile memory device may include a variable sampler configured to process a data signal in an amplifier mode or a sampler mode in response to a control signal, a selection circuit configured to transmit the data signal output from the variable sampler to a flip-flop via a delay unit or to the flip-flop via a path that bypasses the delay unit in response to the control signal, a converter configured to amplify a data strobe signal, a clock distribution network configured to transmit the data strobe signal amplified by the converter to the variable sampler or delay the amplified data strobe signal for a predetermined time and transmit the amplified data strobe signal to the flip-flop in response to the control signal, and a path controller configured to generate the control signal according to an input/output mode.

Nonvolatile memory device providing input/output compatibility and method for setting compatibility thereof

There is provided a semiconductor device, which includes a calibration code generator circuit configured to generate a calibration code according to changes in external conditions, a first driver circuit configured to output a data signal with an impedance value controlled by the calibration code, an emphasis control circuit configured to generate an emphasis data signal using the data signal, and to change the calibration code according to an operating frequency to generate an emphasis code; and a second driver circuit configured to output the emphasis data signal with an impedance value controlled by the emphasis code.

Semiconductor device and method for preforming emphasis driving

An amplifier circuit comprises a first unit circuit and a second unit circuit. The first unit circuit may include a first current mirror circuit that includes a first active inductor including a P-channel transistor, and a first input circuit configured to generate a first differential current and a second differential current based on a pair of differential input signals. The second unit circuit may include a second current mirror circuit that includes a second active inductor including a P-channel transistor, and a second input circuit configured to generate a third differential current and a fourth differential current based on the pair of differential input signals.

Operational transconductance amplifier circuit including active inductor

A semiconductor device has a memory controller configured to provide a data strobe signal, and a memory device configured to receive a data signal provided from the memory controller or output a data signal to the memory controller, wherein the memory device includes a memory interface including a plurality of DQ driving circuits, the memory interface being configured to generate a plurality of phase clock signals based on the data strobe signal, determine a number of phase clock signals provided to the plurality of DQ driving circuits based on an operating frequency of the memory device, and provide the determined number of phase clock signals to the plurality of DQ driving circuits.

Memory interface and semiconductor memory device and semiconductor device including the same

A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

A display apparatus is provided. The display apparatus includes a display and a processor configured to count time for operating a screen saver after a user input is received, and based on the counted time corresponding to a threshold time, control the display to display a screen corresponding to the screen saver by operating the screen saver.

Display apparatus and controlling method thereof

An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

Offset detector circuit for differential signal generator, receiver, and method of compensating for offset of differential signal generator

A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

Receiver including offset compensation circuit

Clock signal delay path unit and semiconductor memory device including the same

Provided are a display apparatus and an operation method thereof for preventing image flicker when displaying mixed images: generating a first image corresponding to video content on a first plane, generating, on a second plane, a second image, outputting a mixed image that is a mixture of the first image and the second image, generating a third image on a third plane corresponding to the mixed image, and displaying the third image based on removal of the first image from the display.

Growing community of inventors

Suwon-si, South Korea

Seungjin Park