Samsung Electronics Co., Ltd.

Seungjin Kim

Gwanghui Lee

Woojun Jung

Minwoo Lee

Seunghyun Oh

Mooyoung Kim

Joonyung Park

Donghyun Yeom

Jaehong Jung

Yoonyoung Choi

Minwoo Kim

Sungjun Lee

Juseok Lee

Jaehoon Lee

Seoyoung Lee

Byunghyun Lee

Jihyun Kim

Junghyun Kim

Byungduk Yang

Taeik Kim

Seungryeol Kim

Byeongjoo Ku

Dongkyun Lee

Baekmin Lim

Joomyoung Kim

Sangjae Park

Kimyung Lee

Jinhyeon Lee

Gihyeok Ha

Yelim Youn

Gyusik Kim

Cheonbae Kim

Hangeol Lee

Jihwan Kim

Jaemin Lee

Minjung Kim

Jungchul An

Kwangtai Kim

Jungbae Kim

Jiyong Kim

Tae-Kyu Kim

Joungmin Cho

Jeon Il Lee

Byung-Hyun Lee

Jinwoo Bae

Hyukwoo Kwon

Hoin Lee

Jung-Bum Lim

Sangdon Jung

Hyun-Sil Hong

Heesook Cheon

Bo-Wo Choi

Byungki Han

Suklae Kim

Kwangrae Cho

Heesoo Son

Hyunsil Hong

Bowo Choi

Sungsoo Yim

Jiesoon Jeong

Wonkang Kim

Kwonsoo Kim

Sangchul Yang

Hyungi Seok

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

Clock integrated circuit including heterogeneous oscillators and apparatus including the clock integrated circuit

A semiconductor device includes a vertical stack of ring-shaped electrodes that are electrically connected together into a top electrode of a capacitor, on a semiconductor substrate. A bottom electrode of the capacitor is also provided, which extends vertically in a direction orthogonal to a surface of the substrate and through centers of the vertical stack of ring-shaped electrodes. An electrically insulating bottom supporting pattern is provided, which extends between a lowermost one of the ring-shaped electrodes and an intermediate one of the ring-shaped electrodes.

Semiconductor devices having highly integrated capacitors therein

An electronic device is provided. The electronic device includes a display driver integrated circuit (IC), a display and a processor configured to receive an interrupt signal from the display driver IC based on a plurality of scanning rates set to a plurality of regions of the display, obtain a plurality of vertical synchronization signals associated with a plurality of regions, based on the received interrupt signal, obtain pieces of content to be displayed in a plurality of regions based on the plurality of vertical synchronization signals, synthesize content based on the coordinate information about the pieces of content, and transmit, to the display driver IC, information about the synthesized pieces of content and information about the remaining pieces of the synthesized content so the synthesized pieces of content and the remaining pieces of the synthesized content are displayed in the plurality of regions.

Electronic device for displaying content on basis of plurality of scanning rates and operating method therefor

An electronic device according to various embodiments comprises: a flexible display including a main display region and at least one extendable display region that can be extended from the main display region; and a processor operatively connected to the display, wherein the processor is configured to: control the display to display first content on the main display having a first size while the electronic device is in a slide-in state, slide the display out to extend same to a second size based on touch input information about the display region being received, control the display to display second content on the extendable display region or the entire display region while the state of the electronic state is being switched into a slide-out state, and complete displaying of the second content and display the first content on at least a part of the display based on switching of the state of the electronic state to the slide-out state being completed.

Seamless screen display during expansion or reduction of a flexible display of an electronic device

An example electronic device may include a display including a main display area and at least one expansion display area expandable from the main display area; and a processor operatively coupled to the display. The processor is configured to, while the electronic device is in a slide-in state, display, on the main display area, a first screen corresponding to an application executed in the slide-in state; based on a portion of the expansion display area being slid out, generate a second screen to be displayed on the main display area and a portion of the slid-out expansion display area; generate a slide effect screen and display the same on at least a portion of the slid-out expansion display area, at least at the same time as the generation of the second screen; and based on the generation of the second screen being completed, remove the display of the slide effect screen and display the second screen on the main display area and the slid-out expansion display area.

Electronic device including flexible display, and screen control method

An electronic device is provided. The electronic device includes a first display disposed on a first surface of the electronic device, a second display disposed on a second surface of the electronic device and having at least a portion thereof being unviewable to a user according to a folding state of the electronic device, a memory configured to store instructions, and a processor electrically connected to the first display, the second display, and the memory. The processor is configured to execute the instructions to detect a change in the folding state of the electronic device while displaying a first image on one of the first display or the second display, when the change in the folding state is detected, generate a second image to be displayed on the other of the first display or the second display, while generating the second image, store a snapshot image of the first image in the memory and display the snapshot image on the other of the first display or the second display, and when the second image is generated, display the second image on the other of the first display or the second display instead of the snapshot image.

Electronic device for seamlessly displaying images, and operating method therefor

A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.

Sub-sampling phase locked loop with compensated loop bandwidth and integrated circuit including the same

An electronic device includes a display including a plurality of regions, a display driver integrated circuit configured to drive a first region of the display at a first driving frequency and drive a second region of the display at a second driving frequency according to a configuration of the display, and a processor configured to provide display data to the display driver integrated circuit. The processor identifies a driving frequency of a first screen to be output on the display in response to reception of a first input; and controls the display to output at least a portion of the first screen on a region, of the plurality of regions, driven at a driving frequency corresponding to the driving frequency of the first screen. The display optimizes driving frequency, thus reducing heating problems and resource waste in the electronic device.

Multi-driving method of display and electronic device supporting same

An electronic device includes a display including a plurality of pixels; a display driver configured to provide a data voltage to the plurality of pixels of the display; and a processor configured to: obtain frequency change-based event information, determine a first frequency and a second frequency higher than the first frequency based on the frequency change-based event information, the first frequency being a target value of a refresh frequency, and provide frame data to the display driver, wherein the processor is further configured to control the display driver to: set a frame section in which the display is driven, during a first frame, generate the data voltage based on the frame data and provide the data voltage to the plurality of pixels, and during a low-frequency driving section, in which the frame data is not obtained, after the first frame, refresh an image based on the second frequency and refresh the image based on the first frequency.

Electronic device comprising display and operation method thereof

An oscillator includes a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency, an injection circuit configured to inject a first injection signal and a second injection signal into the crystal oscillation circuit, a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit, and a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.

Oscillator using sampling PLL-based injection

On an electronic device which includes a display device comprising a display driving circuit, a processor, and a memory a method for changing a refresh rate of the display device includes: changing at least one of a first parameter, a second parameter, or a third parameter in response to identifying the occurrence of at least one of a scan rate change request or a change in scan rate change restriction, and applying the changed parameter among the first parameter, the second parameter, and the third parameter. The first parameter is the frequency of a first synchronization signal generated in the display driving circuit, the second parameter is the increase or decrease in a blank area to substitute for a portion of active video area in frame information, and the third parameter is the frequency of a second synchronization signal for rendering.

Electronic device comprising display, and operation method thereof

A semiconductor device is provided. The semiconductor device includes a plurality of lower electrodes arranged on a semiconductor substrate in a honeycomb structure; and a support connected to the plurality of lower electrodes and defining a plurality of open areas through which the plurality of lower electrodes are exposed. A center point of each of the plurality of open areas is arranged at a center point of a triangle formed by center points of three corresponding neighboring lower electrodes among the plurality of lower electrodes.

Semiconductor device and method of fabricating the same

A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.

Fractional divider with phase shifter and fractional phase locked loop including the same

An electronic device is provided. The electronic device includes a display panel and a display driver integrated circuit configured to drive the display panel. The display driver integrated circuit is configured to determine a luminance value of the display panel if a request for a change from a current driving frequency of the display panel to a target driving frequency is received, and determine at least one intermediate driving frequency between the current driving frequency and the target driving frequency depending on the luminance value of the display panel.

Method of controlling the transition between different refresh rates on a display device

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Hwaseong-si, South Korea

Seungjin Kim