Samsung Electronics Co., Ltd.

Seungjae Jung

Kwang-Ho Park

Jae Hoon Kim

Yong-Hoon Son

Hyunji Song

Gyeonghee Lee

Kiseok Lee

Jaehoon Kim

Sangyeon Han

Taehyun An

Hyungeun Choi

Kwangho Park

Yoosang Hwang

Byungsun Kim

Jong-Ho Moon

Dongjun Oh

Yonghoon Son

Jeongeun Kim

Sanghoon Han

Jungdal Choi

Eun-Ji Kim

Youngbae Kim

Masayuki Terai

Moonyoung Jeong

Sung-Hwan Jang

Jung Moo Lee

Joongchan Shin

Hyoungyol Mun

Han-Sik Yoo

YounSeon Kang

Euichul Jeong

Han-sik Yoo

Youdeuk Kim

A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

Method for forming a three-dimensional semiconductor memory device with an improved etching step

An electronic device includes a display, a housing, a glass panel provided on the display, and a shielding printed layer provided on a second surface of the glass panel in a region corresponding to a space between a side face of the electronic device and an edge of the display. The glass panel includes a flat portion and a curved portion, which includes a first region having a curvature of the curved portion, a second region perpendicular to the first region and covered by the shielding printed layer, and a chamfer region constructed between the first region and the second region. A ratio of a height of the chamfer region with respect to the first region and a length of the chamfer region with respect to the second region has a value in a range of 2 to 4.

Window glass and electronic device including the same

An integrated circuit device includes a plurality of semiconductor layers stacked on a substrate to overlap each other in a vertical direction and longitudinally extending along a first horizontal direction. The plurality of semiconductor layers may have different thicknesses in the vertical direction.

Method of manufacturing integrated circuit device

A memory device includes a substrate and a stack including word lines and interlayer insulating patterns alternatingly stacked on the substrate. The word lines extend in a first direction. Semiconductor patterns cross the word lines and have longitudinal axes parallel to a second direction. The semiconductor patterns are spaced apart from each other in the first direction and a third direction. Bit lines extend in the third direction and are spaced apart from each other in the first direction. Each of the bit lines contacts first side surfaces of the semiconductor patterns spaced apart from each other in the third direction. Data storage elements, which are respectively provided between vertically adjacent interlayer insulating patterns and contact second side surfaces opposite to the first side surfaces, and substrate impurity layers provided in portions of the substrate at both sides of the stack, are included.

Semiconductor memory device and method of fabricating the same

A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

Semiconductor memory device and method for manufacturing the same

A semiconductor memory device may include a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region; a stack provided on the first region of the peripheral circuit structure, the stack including a plurality of first conductive lines extending in a first direction and are vertically stacked; an upper insulating layer covering the stack; an interconnection layer provided on the upper insulating layer; a penetration plug spaced apart from the stack and is provided to penetrate the upper insulating layer to connect the interconnection layer to the peripheral circuits of the peripheral circuit structure; a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction; and a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad.

Semiconductor memory device

A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

A semiconductor memory device, including a first semiconductor pattern, and a second semiconductor pattern separated from the first semiconductor pattern in a vertical direction; a first bit line electrically connected to a first source/drain region of the first semiconductor pattern, and a second bit line electrically connected to a first source/drain region of the second semiconductor pattern; a word line structure in contact with the first semiconductor pattern and the second semiconductor pattern; and a first data storage element electrically connected to a second source/drain region of the first semiconductor pattern, and a second data storage element electrically connected to a second source/drain region of the second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern are monocrystalline, and wherein a crystal orientation of the first semiconductor pattern is different from a crystal orientation of the second semiconductor pattern.

Three-dimensional semiconductor memory device with concave convex separation structures

Integrated circuit device and method of manufacturing the same

A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.

Three-dimensional semiconductor memory device

Growing community of inventors

Suwon-si, South Korea

Seungjae Jung