Samsung Electronics Co., Ltd.

Seunghyung Lee

Yongseok Ahn

Jaybok Choi

Donghoon Kim

Rama Mythili Vadali

Maiyuran Wijay

Jaewon Yu

Oleg Sergeyevich Khoruzhiy

Geunhee Yang

Dusic Yoo

Song Ni

Venkata Rama Krishna Meka

Provided are an image processing circuit, a system-on-chip including the same, and a method of improving quality of a first image. The image processing circuit includes a tuning circuit configured to receive a segmentation map including pixel-by-pixel class inference information of the first image and a confidence map including confidence of the class inference information, determine classes of respective pixels of the first image, correction effects for each pixel of the image, and correction values indicating intensity of the correction effects based on the segmentation map and the confidence map, and generate a correction map based on the classes and the correction values of the respective pixels; and at least one correcting circuit configured to generate an enhanced image by applying correction effects according to the correction values to the respective pixels of the first image based on the correction map.

Image processing circuit, system-on-chip including the same, and method of enhancing image quality

A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.

Integrated circuit device and manufacturing method thereof

Growing community of inventors

Hwaseong-si, South Korea

Seunghyung Lee