Samsung Electronics Co., Ltd.

Seunghyun Oh

Seungjin Kim

Jaehoon Lee

Jaehong Jung

Dongil Yang

Wonsub Lim

Wan Ho Kim

Jiseon Paek

Youngsea Cho

Sangdon Jung

Hyoseok Na

Kyungmin Lee

Daeyoung Kim

Wan Don Kim

Yong Gyu Lim

Barosaim Sung

Sunah Park

Baekmin Lim

Joomyoung Kim

Gyusik Kim

Yelim Youn

Gihyeok Ha

Jinhyeon Lee

Jihwan Kim

Yong Kyun Lim

Hanyeop Lee

Yong Bin Lim

Seonjun Kim

Wonkang Kim

Taegun Noh

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

Clock integrated circuit including heterogeneous oscillators and apparatus including the clock integrated circuit

A deserializer includes a shift register circuit that outputs N output data by shifting input data based on a first clock signal, a clock divider that outputs N second clock signals N-divided from the first clock signal and having N phases different from each other, and outputs one or more third clock signal divided to have a frequency less than that of the second clock signals, a clock selecting circuit that outputs a selected clock signal having an edge corresponding to a second time after N number of clock cycles of the first clock signal have elapsed from a first time at which a valid period is detected in a selection signal for selecting the input data based on the N second clock signals and the one or more third clock signals, and a data align circuit that parallelizes the N output data based on the selected clock signal.

Deserializer and memory module including the same

A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.

Low dropout regulator providing variable offset and analog to digital conversion circuit including the same

A current steering digital-to-analog converter includes a plurality of current cells each including a current source circuit and a current switch circuit to selectively output a current in response to a first input signal corresponding to a digital signal; a dummy current cell including a dummy current source circuit and a dummy current switch circuit to output a current in response to a second input signal; and a current switch bias circuit coupled to the dummy current cell to track a first voltage of an internal node of the dummy current source circuit and configured to generate a first bias voltage applied to the current switch circuit.

Current steering digital-to-analog converter and integrated circuit including the same

A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.

Sub-sampling phase locked loop with compensated loop bandwidth and integrated circuit including the same

An oscillator includes a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency, an injection circuit configured to inject a first injection signal and a second injection signal into the crystal oscillation circuit, a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit, and a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.

Oscillator using sampling PLL-based injection

The electronic device of the present invention may comprise: a first antenna and a second antenna; a communication circuit; and a processor electrically connected to the first antenna, the second antenna, and the communication circuit. The processor is configured to: control the communication circuit such that a first signal is output to the first antenna; acquire a second signal corresponding to the first signal reflected from the first antenna, and a third signal corresponding to the first signal output through the first antenna and received by the second antenna; identify a reflection coefficient at which the first signal is reflected from the first antenna, and a transmission coefficient at which the first signal is transmitted to the second antenna; and perform a designated function according to a value corresponding to a distance between the electronic device and an external object.

Electronic device and method for performing designated function according to distance to external object, determined on basis of signal output through antenna

An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.

Split inverter, capacitor digital-to-analog converter and analog-to-digital converter of successive approximation register type including same

A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.

Fractional divider with phase shifter and fractional phase locked loop including the same

Provided are an analog-to-digital converter and/or an operating method thereof. The analog-to-digital converter includes a sample/hold circuit, a digital-to-analog converter, a comparing circuit, and a control logic circuit, wherein the digital-to-analog converter includes a first capacitor connected to a first comparison node and a first filtering node, a first reference voltage switch connected to the first filtering node and connected to a first delivery node or a first transmission node, a first pre-charge switch connected to the first filtering node or the first delivery node, and a first pre-charge capacitor connected to the first pre-charge switch and a ground voltage.

Analog-digital converter and operating method thereof

A phase locked loop includes a phase detector outputting a first signal corresponding to a phase difference of a reference frequency signal and a division frequency signal, a charge pump amplifying a first signal to output a second signal, a loop filter filtering the second signal to output a third signal, a voltage-to-current converter receiving the third signal and outputting a fourth signal, a digital-to-analog converter outputting a fifth signal based on the fourth signal and a digital compensation signal, an oscillator outputting an output frequency signal having a frequency corresponding to the fifth signal, a divider dividing the frequency of the output frequency signal to output the division frequency signal and a compensation frequency signal, and an automatic frequency calibrator compensating for the voltage-to-current converter based on a difference between a frequency of the compensation frequency signal and a frequency of a reference frequency signal.

Phase locked loop and operating method of phase locked loop

A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.

Comparator providing offset calibration and integrated circuit including comparator

A crystal oscillator reducing phase noise and a semiconductor chip including the same are provided. The crystal oscillator includes a transconductance circuit electrically connected to a crystal, a load capacitor connected to the transconductance circuit, a feedback resistance circuit connected between an input terminal of the transconductance circuit and an output terminal of the transconductance circuit, the feedback resistance circuit configured to provide a feedback resistance, and a variable resistance controller configured to generate a resistance control signal for controlling the feedback resistance, the resistance control signal causing the feedback resistance to have a first value in a first period and a second value in a second period, the first value being less than the second value, the first period corresponding to a first portion of a cycle of the clock signal, and the second period corresponding to a second portion of the cycle different from the first portion.

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Seoul, South Korea

Seunghyun Oh