Globalfoundries Inc.

Seunghwan Seo

Jongsin Yun

Ralf Van Bentum

Joerg Schmid

A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Semiconductor structure including a ferroelectric transistor and method for the formation thereof

An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor.

A circuit for providing additional current in a memory cell without a higher supply voltage is provided. Embodiments include a circuit having a six transistor static random access memory (SRAM) cell including a first inverter and second cross-coupled to a second inverter; a first transistor having a first source coupled to a first bit-line, a first drain coupled to the first inverter, and a first gate coupled to a word-line; a second transistor having a second source coupled to the second inverter, a second drain coupled to a second bit-line, and a second gate coupled to the word-line; and a plurality of bit-line sensing transistors coupled to the first transistor and to the second transistor.

Growing community of inventors

Dresden, Germany

Seunghwan Seo