Samsung Electronics Co., Ltd.

Seunghune Yang

Sooyong Lee

Sangoh Park

Kiho Yang

Sangwook Kim

Dongho Kim

Keunnam Kim

Dongjun Lee

Sibo Cai

Jeeyong Lee

Kaiyuan Chi

Hungbae Ahn

Pilsoo Kang

Jungmin Kim

Jeeeun Jung

Sung Min Nam

Jaeseung Jeong

Sungyong Moon

Changmook Yim

Yangwoo Heo

Mi-Jin Kwon

Hyeyoung Ji

Wonchan Lee

A pitch walk inspection method includes obtaining a scanning electron microscope (SEM) image for a line and space (L/S) pattern formed by a multi-patterning technology (MPT), where L/S pattern includes a plurality of lines and spaces that are alternately arranged; detecting a main pitch of the L/S pattern in the SEM image; dividing a graph of the main pitch into graphs of component pitches, based on the MPT; performing a Fast Fourier Transform (FFT) on each graph of the component pitches; multiplying a phase and an intensity graph of the FFT of each of the graphs of the component pitches with each other and obtaining compensated FFT phase graphs; and calculating a pitch walk for the L/S pattern by obtaining differences between phase peak values of the compensated FFT phase graphs.

Scanning electron microscope image-based pitch walk inspection method and method of manufacturing semiconductor device comprising the inspection method

A method for manufacturing a semiconductor device, includes receiving a first layout including patterns for the manufacturing of the semiconductor device, generating a second layout by performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout, generating a third layout by performing optical proximity correction (OPC) on the second layout, and performing a multiple patterning process based on the third layout. The multiple patterning process includes patterning first-type patterns, and patterning second-type patterns. The machine learning-based process proximity correction is performed based on features of the first-type patterns and features of the second-type patterns.

Method and computing device for manufacturing semiconductor device

A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

Methods of manufacturing semiconductor devices

With respect to each layout pattern of a plurality of layout patterns included in a layout for semiconductor processes, where the layout includes schematic information to form process patterns of a semiconductor device, vertical features indicating an effect of a lower structure on the process patterns are determined, and the lower structure indicates a structure that is formed in the semiconductor device before the process patterns are formed. A machine learning module is trained based on a training layout and the vertical features of the training layout. A design layout with schematic information to form target process patterns is corrected based on the trained machine learning module, the design layout and the vertical features of the design layout. Reliability and integration of the layout for the semiconductor processes may be increased by correcting the layout based on the vertical features and the horizontal features.

Methods and devices of correcting layout for semiconductor processes using machine learning

A mask forming method includes providing preliminary mask data including a Manhattan path such as a quadrangle, a bar, a polygon or a combination thereof based on a layout. Mask data including a curvilinear shape is prepared by correcting the preliminary mask data through application of an elliptical function, a B-spline curve, or a combination thereof. A mask pattern is formed on a mask substrate based on the mask data.

Method of forming mask including curvilinear shape and method of forming semiconductor device

Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

Electronic device for manufacturing semiconductor device and operating method of electronic device

Semiconductor devices having landing pad patterns and methods of manufacturing the same

A method of manufacturing a mask may include identifying an error pattern of final patterns formed on a substrate, correcting a first target pattern on the basis of the error pattern, fracturing a first mask layout into a plurality of first segments on the basis of the corrected first target pattern, and correcting the first mask layout by biasing a plurality of first target segments corresponding to a first final target among the plurality of segments. The first mask layout may include a first extension pattern, final targets disposed in zigzags, and the first final target corresponding to the error pattern, and each of the plurality of first segments may corresponds to one of the final targets.

Method of designing mask layout based on error pattern and method of manufacturing mask

The inventive concepts provide a method for inspecting a pattern, a method for manufacturing a semiconductor device, and an apparatus used according to the methods. The method for inspecting a pattern includes detecting a measured image corresponding to a pattern formed on a substrate, detecting a first hot spot corresponding to a ghost image of the measured image, with the first hot spot representing a defect of the pattern, and detecting a second hot spot that has an area that is wider than that of the first hot spot.

Method for inspecting pattern and an apparatus for manufacturing a semiconductor device using the same

A pattern analysis method of a semiconductor device includes extracting a contour image of material layer patterns formed on a wafer, calculating an individual density value (DV) representing an area difference between the contour image and a target layout image, scoring the material layer patterns on the wafer using the individual DV, identifying a failure pattern among the scored material layer patterns, calculating coordinates of the identified failure pattern and displaying the coordinates on a critical dimension-scanning electron microscopy (CD-SEM) image, inputting a reference DV in the computer and automatically sorting the material layer patterns into material layer patterns having a hotspot and material layer patterns not having a hotspot, and reviewing the sorted material layer patterns having the hotspot.

Pattern analysis method of a semiconductor device

Inventive concepts provide a method of inspecting a semiconductor device including obtaining inspection image data of an inspection pattern of an inspection layer on a substrate. The method may include extracting inspection contour data including an inspection pattern contour from the inspection image data, and merging the inspection contour data with comparison contour data of a comparison layer to obtain merged data. The comparison layer may overlap the inspection layer. The method may also include determining a horizontal distance between the inspection pattern contour and a comparison pattern contour of the comparison contour data based on the merged data.

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Seoul, South Korea

Seunghune Yang