Samsung Electronics Co., Ltd.

Seunghun Shin

Yeongkwon Ko

Junyeong Heo

Yun-Rae Cho

Hyunggil Baek

Donghoon Won

Sundae Kim

Namgyu Baek

Jiwoo Lee

Kwangho Kim

Dongryul Shin

Sooyoung Jang

Chulhyung Yang

Jaejune Jang

Sunwoo Park

Sungkee Kim

Dukseo Park

Joonbo Park

Wowjin Choi

Howoo Park

Junhyuck Lee

Moonhyuk Choi

Hanjae Bae

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

Semiconductor package and method of fabricating the same

A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip.

Semiconductor package having molding layer with inclined side wall

Semiconductor package

A decoupling capacitor includes a first insulating layer extending in a horizontal direction, a storage plate arranged on the first insulating layer, a top plate facing the storage plate, a second insulating layer interposed between the storage plate and the top plate and having a plurality of through holes, a capacitor block including a plurality of capacitor structures in the plurality of through holes, a wiring structure covering the top plate, a first conductive pad arranged on the wiring structure and configured to be electrically connected to the storage plate through a first conductive path of the wiring structure, and a second conductive pad spaced apart from the first conductive pad in the horizontal direction in the same plane as the first conductive pad and configured to be electrically connected to the top plate through a second conductive path of the wiring structure.

Discrete decoupling capacitor and integrated circuit chip package including same

A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

Substrate, method of sawing substrate, and semiconductor device

An electronic device is provided including a housing including a first plate, a second plate facing the first plate, and a side member between the first and second plate, a radio frequency (RF) circuit, a processor, a ground member, a first electric path connected between a first port of the RF circuit and a first point of a first conductive portion of the side member, a second electric path connected between a second port of the RF circuit and a first point of a second conductive portion of the side member, a third electric path connected between a second point of the first conductive portion and the ground member, a fourth electric path connected between a second point of the second conductive portion and the ground member, and a fifth electric path connected between one point of the second electric path and one point of the third electric path.

Electronic device including metal housing antenna

Growing community of inventors

Asan-si, South Korea

Seunghun Shin