Samsung Electronics Co., Ltd.

Nanobrick Co., Ltd.

Seunghun Han

Yunrae Cho

Eunkyul Oh

Taeheon Kim

Sangwon Kim

Boseung Jang

Jaehyun Joo

The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

Semiconductor package and method of fabricating the same

Provided is a method for manufacturing a reflective display particle, the method including: (a) preparing first and second dispersion solutions by dispersing first and second reflective display materials that reflect light in different wavelength ranges into first and second media that contain a curable material and are unmixed with each other, respectively; (b) forming an emulsion by mixing the prepared first and second dispersion solutions, and encapsulating the emulsion into a capsule; and (c) having the first and second dispersion solutions contained in the encapsulated emulsion undergo phase separation, and curing the phase-separated first and second dispersion solutions by applying energy to the phase-separated first and second dispersion solutions.

Reflective display particle, reflective display device, and method for manufacturing the same

Provided are semiconductor packages and methods of fabricating the same. In one embodiment, the package may include an upper package stacked on a lower package, and a plurality of connection terminals electrically connecting the lower and upper packages. The lower package may include a lower package substrate, a lower semiconductor chip mounted on the lower package substrate, and a lower mold layer provided on the lower package substrate to mold the lower semiconductor chip. The lower mold layer may have a trench-shaped first opening through which the lower package substrate is exposed in a substantially line shape. The connection terminals may be electrically connected to the lower package substrate exposed by the first opening and be not in contact with the lower mold layer.

Semiconductor packages having trench-shaped opening and methods for fabricating the same

Growing community of inventors

Suwon-si, South Korea

Seunghun Han