Lg Display Co., Ltd.

Seungho Heo

Byeongseong So

Sungwook Yoon

Donghyun Lee

Chung Hoon Lee

Yousung Nam

Seungwan Cho

ByoungHyun Koo

Daeseok Oh

Saichang Yun

Hyunguk Jang

SungWook Yoon

DongMin Jang

Changdeok Lee

JeongGi Yun

Juneho Park

Sangdeok Ha

Beong-Ho Lee

A display apparatus includes a substrate on which a plurality of sub-pixels is defined, a plurality of anodes disposed in each of the plurality of sub-pixels on the substrate, an organic layer disposed on the plurality of anodes, a cathode disposed on the organic layer, and a bank disposed between the anode and the organic layer and between emission areas of each of the plurality of sub-pixels. The bank includes a plurality of trenches, and the organic layer and the cathode are disposed in the bank and the plurality of trenches. As a result, a resistance of the organic layer in which a leakage current flows from the trench increases, so that the leakage current which may be transmitted to the adjacent sub-pixels and color mixing due to the leakage current can be minimized.

Display apparatus

Provided is a display apparatus that includes a substrate in which a plurality of sub pixels are defined; a plurality of light emitting diodes which are disposed in the plurality of sub pixels, the plurality of light emitting diodes having an organic layer shared between the plurality of light emitting diodes and a cathode electrode shared between the plurality of light emitting diodes; a bank disposed below the cathode electrode and between pairs of light emitting diodes from the plurality of light emitting diodes; a plurality of wiring lines disposed between the bank and the substrate; and a first pattern through a thickness of the bank, the first pattern overlapping a first wiring line from the plurality of wiring lines, wherein a first portion of the cathode electrode is disposed outside of the first pattern and a second portion of the cathode electrode is disposed in the first pattern.

According to an aspect of the present disclosure, a display apparatus includes a substrate in which a plurality of sub pixels is defined; a plurality of light emitting diodes which are disposed in the plurality of sub pixels, share a common organic layer and a cathode, and have an emission layer and an anode which are separated, respectively; a conductive layer disposed between the plurality of sub pixels; and a bank which is disposed below the cathode between the plurality of light emitting diodes and exposes the anode and the conductive layer. The plurality of sub pixels include a first sub pixel and a second sub pixel having a turn-on voltage lower than that of the first sub pixel, and the conductive layer is disposed to be closer to the second sub pixel between the first sub pixel and the second sub pixel.

A display device comprises a pixel array, a timing controller, a Q node control signal input line, and a shift register. In the pixel array, data lines and gate lines are defined, and pixels are arranged in a matrix. The timing controller outputs a start signal and a first reset signal. The Q node control signal input line receives the start signal and the first reset signal. The shift register comprises a plurality of stages connected as a cascade, and sequentially supplies dummy gate pulses or gate pulses applied to the gate lines.

Gate driver and display device having the same

A display device includes a display panel and a shift register generating a gate pulse and sequentially outputting the gate pulse to gate lines in response to a voltage at a Q node of each of dependently connected stages. An nth (n is a natural number) stage of the shift register includes a pull-up transistor, a start controller, a reset controller, and a first reset output terminal controller. A first reset output controller outputs a reset signal to a reset signal output terminal at a timing at which a second clock signal and a first output control signal output in a non-display period are synchronized.

Display device

Disclosed is a display device that may include a display panel, a data driver configured to supply a data signal to the display panel, and a scan driver formed in a non-display area of the display panel, including a shift register composed of a plurality of stages and a level shifter formed outside the display panel, and configured to supply a scan signal to the display panel using the shift register and the level shifter, wherein the shift register is arranged in an output terminal of an N-th stage circuit unit formed in a first non-display area and an output terminal of an N-th compensation circuit unit formed in a second non-display area opposite the first non-display area are paired to be connected to an N-th scan line, wherein the N-th compensation circuit unit outputs a compensation signal to the N-th scan line in response to a node voltage of a neighboring stage circuit unit.

Scan driver ADN display device using the same

The present disclosure relates to reducing bezel area of a flat display panel comprising a substrate with a non-display area surrounding a display area, the display area comprising common lines coupled to corresponding rows of pixels; and a gate driver formed in the non-display area. The display may further include a conductive sealing region formed in the non-display area and configured to supply a common line voltage; and a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply a common line voltage to the rows of pixels. Alternatively, the display may further include a vertical common line formed in the non-display area between the gate driver and the display area, the vertical common line extending from top to bottom of the non-display area and coupled to said common lines to apply a common voltage.

Flat display panel having narrow bezel

A liquid crystal display includes according to an embodiment a display panel provided with a plurality of data lines, a plurality of gate lines intersecting the data lines, liquid crystal cells arranged in a matrix, and TFTs disposed at the intersections of the data lines and the gate lines; source drive ICs configured to supply data voltages to the data lines, wherein polarities of data voltages are reversed by a column inversion scheme; and a gate driver configured to sequentially supply gate pulses for the gate lines, wherein polarities of the data voltages charged in the liquid crystal cells in the display panel are reversed in dot unit.

Growing community of inventors

Paju-si, South Korea

Seungho Heo