University of Michigan

Seungheun Song

Michael P Flynn

Justin Correll

Matthew R Belz

Lu Jie

Seungjong Lee

A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.

Sub-sampling phase locked loop (SSPLL) with saturated reference feedback

Crossbar arrays perform analog vector-matrix multiplication naturally and provide a building block for modern computing systems. Specialized mixed-signal interface circuits are interfaced with the rows and columns of the crossbar arrays. During operation, the mixed-signal interface circuits provide high voltages for write operations and low voltages for read operations. This disclosure presents improved designs for the mixed-signal interface circuits which minimize the number of switches as well as the number level shifters.

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Ann Arbor, MI, United States of America

Seungheun Song