Samsung Electronics Co., Ltd.

Seunghee Mun

Dohyung Kim

Hwanwook Park

Dongyoon Seo

Wonseop Lee

Jeonghoon Baek

Jinoh Ahn

A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kmodule clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)module clock signal terminal; and a fourth signal line for connecting the (k+1)module clock signal terminal to a 2kmodule clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

Growing community of inventors

Yongin-si, South Korea

Seunghee Mun