Samsung Electronics Co., Ltd.

Korea Advanced Institute of Science and Technology

Sungkyunkwan University

Seungchul Jung

Sang Joon Kim

Sangjoon Kim

Sungmeen Myung

JongPal Kim

Hyungwoo Lee

Yongmin Ju

Seok Ju Yun

Hankyu Lee

Wonseok Lee

Yeunhee Huh

Chang Soon Park

Gyu-Hyeong Cho

Junyoung Park

Jong Wook Lee

Jong Pal Kim

Gyu Hyeong Cho

Jaehyuk Lee

Jaechun Lee

Seungkeun Yoon

Boyoung Seo

Daekun Yoon

Min Seong Choi

Yoonmyung Lee

Kangho Lee

Dae-Geun Jang

Sang Jin Lim

Seok Tae Koh

Se Un Shin

Hyungmin Gi

Yu Jin Yang

Kye-Seok Yoon

Seok Tae Kho

A neuromorphic device includes a plurality of resistor lines, each comprising a plurality of resistors that are serially connected to each other; one or more current sources configured to control a current flowing in each of the resistor lines to a respective current value; a plurality of capacitors configured to be electrically connected to each of the resistor lines and to sample respective voltage of each of the resistor lines representing results of neuromorphic operations; and a switch configured to connect the plurality of the capacitors in parallel after the sampling the respective voltage of each of the resistor lines, to output a sum of the results of neuromorphic operations.

Neuromorphic device and driving method thereof

A neural network apparatus includes: a plurality of memory cells each comprising a variable resistance element and a first transistor; a plurality of bit lines extending in a first direction; and a plurality of word lines extending in a second direction, crossing the bit lines and respectively connected to the first transistor of the plurality of memory cells; a plurality of sub-column circuits each comprising memory cells of the memory cells connected in parallel along the first direction; and a column circuit comprising two or more of the sub-column circuits connected in series along the second direction, wherein, when a neural network operation is performed, the column circuit outputs a summation current to a bit line connected to the column circuit based on voltage applied to the plurality of word lines.

Neural network apparatus

A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.

Computing device for performing digital pulse-based crossbar operation and method of operating the computing device

A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.

Memory and method with in-memory computing defect detection

A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.

Processing device and electronic device having the same

A neuromorphic device includes a first resistor line having a plurality of first resistors that are serially connected to each other, a second resistor line having a plurality of second resistors that are serially connected to each other, one or more current sources to control a current flowing in each of the first resistor line and the second resistor line to a respective current value, a first capacitor electrically connectable to the first resistor line, and a second capacitor electrically connectable to the second resistor line.

A multi-bit cell includes: a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance; a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to output one signal of the weight voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store a respective weight capacitance, and to generate charge data by performing an operation on the outputted signal and the weight capacitance.

Device and method with multi-bit operation

Provided is method and apparatus with memory array programming. A memory apparatus may include a memory array including memory cells, and a memory controller, where the memory controller is configured to configured to repeat, for a plurality of times, a generation of a first present time current error between a first present time current and a first target current, both of a first memory cell, a generation of a second present time current error between a second present time current and a second target current, both of a second memory cell, where a greatest among the first present time current error and the second present time current error is a greatest present time current error, and a programming of a select one of the first and second memory cells that has the greatest present time current error.

Method and apparatus with memory array programming

A power providing device is provided. The power providing device includes a first energy harvester element configured to generate power in response to an external energy signal being received, a connection switching element configured to switch a connection between the first energy harvester element and a second energy harvester element; and a first rectifier comprising one or more path switching elements configured to change a rectification path in response to the switching of the connection switching element, wherein the first rectifier is connected to the first energy harvester element to rectify the power generated by the first energy harvester element along the rectification path.

Method and apparatus that provides power generated from external energy signal

A converter and a circuit device including the converter are disclosed. The converter includes an inductor including a first end and a second end, and a switching circuit connected to the inductor. The switching circuit includes a first switch to control a connection between the first end and a battery connected to the converter, a second switch to control a connection between the second end and a current output end configured to output a current generated through the inductor from the battery, a third switch to control a connection between the second end and a voltage output end configured to output a voltage generated from the battery, and a fourth switch to control a connection between the second end and a voltage input end configured to receive a voltage to charge the battery.

Converter device and method

A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.

Method and apparatus performing operations using circuits

An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.

Apparatus and method with in-memory delay dependent processing

Provided is a processing device having improved reliability and power consumption efficiency of analog calculations as well as high cost efficiency due to reduction in a size of a bit-cell, and an electronic system including the processing device. The processing device includes: at least one bit-cell line on which a plurality of bit-cells are connected to each other in series, wherein each of the bit-cells includes: a first magnetic tunnel junction (MTJ) element; a second MTJ element connected to the first MTJ element in parallel; a first switching element connected to the first MTJ element in series; and a second switching element connected to the second MTJ element in series, and wherein on the bit-cell line, two adjacent bit-cells are connected to each other in series in a mirroring structure.

Processing device based on magnetic tunnel junction (MTJ) element and electronic system including the processing device

A wireless power receiver and a wireless power reception method are disclosed. The wireless power receiver includes a charging element, a receiving coil configured to wirelessly receive power from a wireless power transmitter, a rectifier configured to convert an alternating current (AC) voltage generated from the receiving coil to a direct current (DC) voltage, and to output the DC voltage, a voltage converter configured to generate a charging current to charge the charging element, based on the DC voltage output from the rectifier, a current measurer configured to measure the charging current transferred to the charging element, and a controller configured to control a level of the charging current generated from the voltage converter based on a result of the measuring.

Device and method for receiving power wirelessly

Provided are processing and an electronic device including the same. The processing apparatus includes a bit cell line comprising bit cells connected in series, a mirror circuit unit configured to generate a mirror current by replicating a current flowing through the bit cell line at a ratio, a charge charging unit configured to charge a voltage corresponding to the mirror current as the mirror current replicated by the mirror circuit unit is applied, and a voltage measuring unit configured to output a value corresponding to a multiply-accumulate (MAC) operation of weights and inputs applied to the bit cell line, based on the voltage charged by the charge charging unit.

Growing community of inventors

Suwon-si, South Korea

Seungchul Jung