Fairchild Korea Semiconductor Ltd.

Fairchild Semiconductor Corporation

Fiarchild Korea Semiconductor, Ltd

Seung-Yong Choi

O-seob Jeon

Joo-yang Eom

Maria Cristina B Estacio

Seung-won Lim

Ti Ching Shian

Min-hyo Park

Seung-Won Lim

Eul-bin Im

Byeong Gon Kim

Gi-young Jeon

Jonathan A Noquil

Seung-jin Kim

A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.

Flip chip MLP with conductive ink

Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

Heat sink package

Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.

Semiconductor package formed within an encapsulation

A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead frame or a heat sink and the semiconductor chips disposed thereon.

Multi-chip package

The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device to the leads and an encapsulation layer protects the package. In a second embodiment, the MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package according to each embodiment.

A power module flip chip package is provided. The power module flip chip package includes a package carrier having a front surface and a back surface facing the front surface, and a power semiconductor device electrically connected to the front surface of the package carrier via conductive bumps. The conductive bumps are electrically connected to a gate terminal, a source terminal, and a drain terminal of the power semiconductor device. The power module flip chip package has reduced resistance and inductance and improved reliability.

Power module flip chip package

A stacked intelligent power module package is provided. The intelligent power module package of the present invention includes a power unit including a heat sink and a control unit which is separately manufactured from the power unit and is subsequently stacked on the power unit. The power unit and the control unit of the intelligent power module package are stacked in two different ways including stacking two wire-bonded leadframes of the power unit and the control unit and stacking two separate semiconductor packages of the power unit and the control unit by using locking means formed in each of the semiconductor packages after a trimming/forming process and an electrical property test are finished.

Growing community of inventors

Seoul, South Korea

Seung-Yong Choi