Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Seung Yeop Kook

Sung Won Jeong

Shang Hoon Seo

Ji Hoon Kim

Ha Young Ahn

Sun Ho Kim

Ji Hyun Lee

Young Gwan Ko

Kyoung Moo Harr

Jin Su Park

Seung Eun Lee

Myung Sam Kang

Yul Kyo Chung

Young Kwan Lee

Chul Jun Choi

Joo Hwan Jung

Christian Romero

Ju Hee Park

Dae Young Jung

A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer, and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. At least a portion of a first wall of a first trench of the first insulating layer and at least a portion of a second wall of a second trench of the second insulating layer overlap each other vertically. At least a portion of the second wall of the second trench and at least a portion of a third wall of a third trench of the third insulating layer overlap each other vertically.

Fan-out semiconductor package and electronic device including the same

A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.

An electronic component package includes a wiring part including an insulating layer, a conductive pattern formed on the insulating layer, and a conductive via connected to the conductive pattern through the insulating layer, an electronic component disposed on the wiring part, a frame disposed on the wiring part and having a component disposition region defined by an inner wall of the frame surrounding the electronic component, and an encapsulant filling at least a portion of the component disposition region. A portion of the inner wall of the frame forms a protrusion protruding toward the electronic component.

Electronic component package having stress alleviation structure

The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.

Fan-out semiconductor package and method of manufacturing same

A substrate for a camera module includes: a first substrate; an image sensor installed on the first substrate and a memory chip installed to be embedded in the first substrate. The first substrate includes a soft substrate portion disposed at a central portion of the first substrate, and a hard substrate portion formed on upper and lower portions of the soft substrate portion, and at least a portion of the memory chip is disposed in an installation hole formed in the soft substrate portion.

Substrate for camera module and camera module having the same

A fan-out semiconductor package and an electronic device including the same are provided. The fan-out semiconductor package includes a semiconductor chip; an interconnection member electrically connected to the semiconductor chip and having a connection terminal pad; and a passivation layer disposed at one side of the interconnection member and having an opening part opening a portion of the connection terminal pad. Distances from a center of the connection terminal pad to at least two points of an edge thereof are different from each other.

An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal connection pads, a passivation layer disposed on one side of the redistribution layer and having openings exposing at least portions of the terminal connection pads, and connection terminals disposed in the openings of the passivation layer and connected to the terminal connection pads. At least one of the openings of the passivation layer has a plurality of protrusion parts.

Electronic component package and electronic device including the same

Disclosed herein are a coreless board for a semiconductor package and a method of manufacturing the same. The coreless board for the semiconductor package includes: a support; a build-up layer formed on the support; an external connection terminal formed on the build-up layer; and a solder resist layer formed on the build-up layer so as to expose the external connection terminal.

Growing community of inventors

Suwon-si, South Korea

Seung Yeop Kook