Skhynix Inc.

Seung Yeol Lee

Jung Soo Kim

Chang Hoon Lee

A fail data augmentation device may input a plurality of fail data units to a data augmentation model, obtain a plurality of augmented fail data units outputted from the data augmentation model, and delete one or more of the augmented fail data units. The plurality of fail data units and the plurality of augmented fail data units includes a first parameter indicating one of a plurality of banks included in a random access memory, a second parameter indicating one of a plurality of matrices included in the bank corresponding to the first parameter, and a third parameter indicating one of a plurality of hex units included in the matrix corresponding to the second parameter respectively.

Fail data augmentation device and method for random access memory

A memory controller includes a test controller, a test information storage, and a machine learning processor. The test controller performs a test on a memory device using a target pattern selected from among a plurality of test patterns in each of a plurality of test modes in which voltage and time conditions of test signals are set differently. The test information storage stores test result information including values associated with fail bits of the memory device measured in the test. The machine learning processor detects a defect acceleration mode in which a defect of the memory device is accelerated, among the plurality of test modes, in the test performed using the target pattern on the basis of the test result information.

Memory controller and operating method thereof

A multi-chip package may include a controller, a storage memory and a buffer memory. The controller may be configured to output a control signal. The storage memory may be tested in response to the control signal. The buffer memory may be sequentially tested while or after testing the storage memory in response to the control signal.

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Icheon-si, South Korea

Seung Yeol Lee