Skhynix Inc.

Seung Wook Oh

Young Suk Seo

Da In Im

Jin Il Chung

Woongrae Kim

Geun Ho Choi

Hyun Seung Kim

Chang Hyun Kim

Min Su Park

Jae Il Kim

Jin Youp Cha

Young Hoon Kim

Young Jae An

Woong Rae Kim

Woo Jin Kang

An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

Electronic device and electronic system related to performance of a termination operation

A semiconductor system includes a memory controller and a memory apparatus. The memory controller provides at least first to third command address signals. The memory apparatus performs a burst read operation based on the first and second command address signals, and terminates the burst read operation by receiving the third command address signal twice. The memory apparatus continuously initializes an internal circuit that is performing the burst read operation in a section the third command address signal is received twice.

Memory apparatus, a semiconductor system including the same and an operating method thereof

A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Skew compensation circuit and semiconductor apparatus including the same

An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.

Electronic device to perform read operation and mode register read operation

A signal driver includes a first driver, a second driver, an on-timing control circuit, and an off-timing control circuit. The first driver is configured to generate a first driving pulse signal by inverting and driving an input pulse signal. The second driver is configured to generate a second driving pulse signal by inverting and driving the first driving pulse signal. The on-timing control circuit is configured to pull-up drive or pull-down drive the first driving pulse signal based on a first on-timing control signal, a second on-timing control signal, and the input pulse signal. The off-timing control circuit is configured to pull-up drive or pull-down drive the second driving pulse signal based on a first off-timing control signal, a second off-timing control signal, and the first driving pulse signal.

Signal generation circuit synchronized with a clock signal and a semiconductor apparatus using the same

A semiconductor device includes an internal clock generation circuit, a command generation circuit, and an address generation circuit. The internal clock generation circuit generates a command clock signal and an inverted command clock signal, wherein a cycle of the command clock signal and a cycle of the inverted command clock signal are determined by a mode. The command generation circuit generates a first command based on a first internal control signal and the command clock signal and generates a second command based on a second internal control signal and the inverted command clock signal. The address generation circuit generates a latch address based on the first internal control signal or a second internal control signal.

Semiconductor devices

A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.

Command generation method and semiconductor device related to the command generation method

A signal generation circuit generates a first synchronization signal by delaying a first input signal in synchronization with a first division clock signal, and generates a second synchronization signal by delaying a second input signal in synchronization with a second division clock signal. The signal generation circuit adjusts pulse widths of the first and second synchronization signals based on an on-control signal and an off-control signal. The signal generation circuit includes a retiming circuit configured to generate an output signal by retiming a preliminary output signal, generated from the first and second synchronization signals, based on the first and second division clock signals.

A semiconductor apparatus includes a clock path, a command path, a delay monitoring circuit, and an output control circuit. The clock path generates a delay clock signal by delaying a clock signal. The command path generates an output command signal from on one of a command signal and the clock signal, based on a monitoring signal. The delay monitoring circuit generates a delay control signal and a latency control signal based on a phase difference between the delay clock signal and the output command signal, when the monitoring signal is enabled. The output control circuit generates an output enable signal by synchronizing the output command signal with the delay clock signal, based on the latency control signal.

Semiconductor apparatus capable of synchronizing command signal and clock signal, and operation method thereof

A strobe signal generation circuit includes a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal; a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; and a second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal from among the at least one pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal.

Strobe signal generation circuit and semiconductor apparatus including the same

A semiconductor device includes a command synthesis circuit synchronized with a first division clock signal to shift a command based on an offset signal and synchronized with a second division clock signal to generate a command synthesis signal from the shifted command. The semiconductor device also includes a strobe control signal synthesis circuit synchronized with the second division clock signal to generate a strobe synthesis signal from a strobe control signal. The semiconductor device further includes a drive control circuit generating a drive control signal from any one of the command synthesis signal and a drive signal based on the strobe synthesis signal.

A memory apparatus may include a plurality of ranks commonly coupled to an input/output (I/O) terminal. Non-target ranks other than a target rank among the plurality of ranks may be configured to perform an on die termination operation based on a read operation of the target rank.

Memory apparatus relating to on die termination

A data strobing circuit may include: an operating speed detection unit configured to detect an operating speed of a semiconductor apparatus according to a clock signal, and generate a control signal with a different value depending on the detected operating speed; and a strobe signal generation unit configured to adjust a delay time and pulse width of a read pulse according to the control signal and output an adjusted signal as a strobe signal.

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Yongin-si, South Korea

Seung Wook Oh