Samsung Electronics Co., Ltd.

Electronics and Telecommunications Research Institute

Seoul National University

Snu Rdb Foundation

Industry-University Cooperation Foundation Hanyang University

University of Iowa Research Foundation

Korea Atomic Energy Research Institute

Melfas Inc.

Nplanic Co., Ltd.

Snu R&db Foundation

Seung Wook Lee

Bon Ki Koo

Joong Baik Kim

Ji Hyung Lee

Il Kyu Park

Ho Won Kim

Bon Woo Hwang

Kyoung Hoon Kim

Chang Woo Chu

Jin Seo Kim

Bo Youn Kim

Yoon-Seok Choi

Jeong Ig Song

Ji Young Park

Hyung-Dal Kwon

Hee Jeong Kim

Seong Jae Lim

In Choon Yeo

Il Ho Lee

Soon Wan Kwon

Jin Sung Choi

Sunjung Lee

Soojung Ryu

Jung Ho Ahn

Young Jik Lee

Kap Kee Kim

Hanmin Park

Jaehyeong Sim

Jintaek Kang

Tae Jun Ham

Jae-Eon Jo

Jae Wook Lee

JangWoo Kim

Hweesoo Kim

Pyeongsu Park

Jaewook Lee

Do Hyung Kim

Kyung Ho Lee

Ge Wang

Jaejin Lee

Jeong Woo Lee

Chang Joon Park

Yong Kim

Ho Young Kim

Jung Chak Ahn

Tae Hun Lee

Ki Nam Kim

Tae-Joon Kim

Jong Eun Park

Euee Seon Jang

Tae Joon Kim

Jeung Chul Park

Hee Geun Jeong

Gil Haeng Lee

Seung Hyup Shin

Seung Uk Yoon

Yi Tae Kim

Myung Kook Moon

Wookeun Jung

Young Hwan Oh

Yong Chil Seo

Nam Ho Lee

Byung Sang Rhim

Jung Ki Jo

Kyu Sung Cho

Sung Ryull Sohn

Younghwan Oh

Tae Ho Lim

Taejun Ham

Jaeyeon Won

Young Gwan Hwang

Hae Young Park

Byoung Ik Kang

Soon Yong Park

Sung Yul Park

Seng Hak Kim

Sam Son

Yunho Jin

Hong Sang Moon

Hong Yong Choi

Bong-Kyung Chun

Won-Il Hwang

Dong-Sung Ryu

Seong Jae Lin

Hwan-gue Cho

Giseok Son

Jaebum Jun

Seung Chan Oh

Kyoung Soo Son

Byoungjun Kim

Daiyong Kim

Yoon Je Lee

Min Seung Baik

An apparatus with deep learning includes: a systolic adder tree including adder trees connected in row and column directions; and an input multiplexer connected to an input register of at least one of the adder trees and configured to determine column directional data movement between the adder trees based on operation modes.

Method and apparatus with deep learning operations with adder tree structure

A processor, a method of operating the processor, and an electronic device including the processor are disclosed. The method includes arranging, in respective input registers, weights and activations having a smaller number of bits than a minimum operation unit of an operator included in the processor, performing a multiplication between values stored in the input registers, storing a result of the multiplication in an output register, and outputting, from the output register, a value in a preset bit range as a result of a dot product between a first vector including the weights and a second vector including the activations.

Processor, method of operating the processor, and electronic device including the same

A scheduler, a method of operating the scheduler, and an accelerator apparatus including the scheduler are disclosed. A method of operating a scheduler to perform scheduling on models to be executed in an accelerator, the method includes receiving at least one execution request for a first model and a second model that are executed independently from each other in the accelerator, and performing layer-unit scheduling on the first model and the second model based on workload characteristics of the first model and the second model.

Scheduler, method of operating the same, and accelerator apparatus including the same

An electronic device includes: a host processor configured to control an operation of the electronic device; accelerators of heterogeneous hardware types configured to exchange data with each other through direct communication; and a control unit configured to convert a command received from the host processor, based on a type of each of the accelerators and transfer a result of the converting to a corresponding accelerator among the accelerators.

Electronic device including accelerators of heterogeneous hardware types for scheduling operation

A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

Computing device and method for allocating resources using cost matrix

An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned on an accelerator, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.

Operation method of an accelerator and system including the same

A scheduler, a method of operating the scheduler, and an electronic device including the scheduler are disclosed. The method of operating the scheduler configured to determine a model to be executed in an accelerator includes receiving one or more requests for execution of a plurality of models to be independently executed in the accelerator, and performing layer-wise scheduling on the models based on an idle time occurring when a candidate layer which is a target for the scheduling in each of the models is executed in the accelerator.

Layer-wise scheduling on models based on idle times

An electronic device includes: a host box comprising a host processor configured to control an operation of the electronic device, a host motherboard in which the host processor is disposed, and a host power supply unit (PSU) configured to supply power to a component connected to the host motherboard; and one or more extension boxes controlled by the host box, wherein each of the one or more extension boxes comprises an extension motherboard independent of the host box, and an extension PSU independent of the host box and configured to supply power to a component connected to the extension motherboard.

Electronic device including host box and one or more extension boxes

An accelerator includes: a memory configured to store input data; a plurality of shift buffers each configured to shift input data received sequentially from the memory in each cycle, and in response to input data being stored in each of internal elements of the shift buffer, output the stored input data to a processing element (PE) array; a plurality of backup buffers each configured to store input data received sequentially from the memory and transfer the stored input data to one of the shift buffers; and the PE array configured to perform an operation on input data received from one or more of the shift buffers and on a corresponding kernel.

Accelerator and electronic device including the same

A memory device includes a memory configured to store input data and filter data for a convolution operation, and a function processor configured to, in response to a read command of at least a portion of data from among the input data and the filter data, transform the at least a portion of the data based on a parameter of the convolution operation during a clock cycle corresponding to the read command and output a corresponding transformation result as transformed data.

Memory device and method

An accelerator, an operation method of the accelerator, and an accelerator system including the accelerator are disclosed. The operation method includes receiving one or more workloads assigned by a host controller, determining reuse data of the workloads based on hardware resource information and/or a memory access cost of the accelerator when a plurality of processing units included in the accelerator performs the workloads, and providing a result of performing the workloads.

A processor-implemented accelerator method includes: reading, from a memory, an instruction to be executed in an accelerator; reading, from the memory, input data based on the instruction; and performing, on the input data and a parameter value included in the instruction, an inference task corresponding to the instruction.

Accelerator, method of operating the same, and electronic device including the same

An access sheath is provided. The access sheath comprises: an outer sheath extending in one direction and having a cavity formed along a longitudinal axis of the outer sheath; and an inner sheath arranged in the cavity of the outer sheath, and having a plurality of balloons configured to expand, wherein the outer sheath includes: an outer body formed of a first material; and an elastic connection part formed of a second material which is more flexible than the first material of the outer body, and wherein a diameter of the outer sheath increases by the elastic connection part which expands according to an expansion of the balloons.

Access sheath

A method and a system for generating a 3D image of a character through steps of: receiving an identifier of a template and a two-dimensional (2D) image of the character generated based on the template corresponding to a type of the character; acquiring template information of the template from a template library by using the identifier, and extracting an effective parameter for machine learning to be performed to generate the 3D image based on the template information and the 2D image; and generating the 3D image of the character by performing the machine learning based on the effective parameter and the template information are provided.

Method and system for generating 3D image of character

Growing community of inventors

Suwon-si, South Korea

Seung Wook Lee