Boe Technology Group Co., Ltd.

Beijing Boe Optoelectronics Technology Co., Ltd.

Ordos Yuansheng Optoelectronics Co., Ltd.

Seung Woo Han

Guangliang Shang

Yuanbo Zhang

Haoliang Zheng

Xing Yao

Mingfu Han

Zhichong Wang

Yun Sik Im

Lijun Yuan

Jing Lv

Yinglong Huang

Jiha Kim

Xue Dong

Jiayang Zhao

Wei Qin

Ruoyu Ma

Xiangxiang Zou

Yanfeng Wang

Hyun Sic Choi

Yoon Sung Um

Zhihe Jin

Jung Mok Jun

Jung Chul Gyu

Im- Yun- Sik

Haifeng Jin

A shift register unit and a driving method, a grid driving circuit and a display device are disclosed. A shift register unit includes an input circuit, a first reset circuit, and an output circuit. The input circuit includes an input terminal configured to perform a first control on the first control node and the first node in response to an input signal of the input terminal, and then perform a second control on the first node under the control of the level of the first node, the first node is located in a path where the input signal incurs the first control; the first reset circuit is configured to reset the first control node in response to the first reset signal; the output circuit is configured to output an output signal to an output terminal under the control of the level of the first control node.

Shift register unit and driving method thereof, gate drive circuit and display device

The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.

Array substrate gate driving unit and apparatus thereof, driving method and display apparatus

Embodiments of the present application provide a shift register unit, a method for driving the same, a gate driving circuit, and a display apparatus. The shift register unit comprises at least two sub-circuits of a first output sub-circuit, a second output sub-circuit, and a third output sub-circuit. The first output sub-circuit is configured to output a voltage at a signal output terminal to a reset signal output terminal; the second output sub-circuit is configured to output the voltage at the signal output terminal to a gating signal output terminal; and the third output sub-circuit is configured to output a voltage at a second voltage terminal to a light-emitting control signal output terminal or is configured to output a voltage at a first voltage terminal to the light-emitting control signal output terminal.

Shift register unit and method for driving the same, gate driving circuit, and display apparatus

An array substrate, a display panel, a display device and a driving method. The array substrate includes: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit a second gate driving circuit; a plurality of first gate lines connected with the first gate driving circuit; and a plurality of second gate lines connected with the second gate driving circuit. A first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion is connected with one of the plurality of first gate lines; and a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion is connected with one of the plurality of second gate lines.

Array substrate, display panel, display device and driving method

There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.

Shift register unit, gate driving circuit, display and gate driving method

The present disclosure relates to a pixel driving circuit for switching display resolution, a driving method thereof, and a display apparatus. The pixel driving circuit comprises: r first data lines and k second data lines, each of the first data lines has a first switch provided thereon, and is connected to at least one of the k second data lines through at least one second switch respectively, and the first switch and the second switch are connected to a signal control unit which is configured to control the first switch to be turned on and the second switch to be turned off when display is to be performed at a first resolution, and control the first switch to be turned off and the second switch to be turned on when display is to be performed at a second resolution.

Pixel driving circuits for switching display resolution, driving methods thereof and display apparatuses

A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

Shift-buffer circuit, gate driving circuit, display panel and driving method

The present disclosure discloses a GOA unit driving circuit and a driving method thereof, a display panel and a display device. The disclosure relates to field of display technology, and solves the technical issue of increased power consumption of the display device due to the power consumption of the parasitic capacitance existing in the transistors in the GOA unit. The GOA unit driving circuit comprises a plurality of sets of GOA units, each of which includes at least one GOA unit; a plurality of clock selecting units, which are in one-to-one correspondence with the plurality of sets of GOA units, and each clock selecting unit is connected to a corresponding set of GOA units and connected to one of a plurality of clock signal terminals and at least one of a plurality of clock selection signal terminals, respectively. An intersection of any two sets of GOA units in the plurality of sets of GOA unit is an empty set, and each clock selecting unit transmits a signal of the clock signal terminal to which the clock selecting unit is connected to the corresponding set of GOA units, under control of a signal of the at least one clock selection signal terminal to which the clock selecting unit is connected. The GOA unit driving circuit provided by the present disclosure may be applied to a display device.

GOA unit driving circuit and driving method thereof, display panel and display device

An inverter and a method for driving the inverter, a gate driver on array (GOA) unit, a GOA circuit and a display device relate to a technical field of display, and are proposed to supply stable inverter output signal. The inverter comprises a control module and an output module. The control module is configured to control a voltage at a control node under the control of a first clock signal at a first clock signal terminal, a second clock signal at a second clock signal terminal, an input signal at an input terminal and voltages at a first level terminal and a second level terminal. The output module is configured to set a voltage at the output terminal to the voltage at the first level terminal or the voltage at the second level terminal under the control of the control node and the input signal at the input terminal.

Inverter and method for driving the inverter, gate on array unit and gate on array circuit

A shift register unit, gate driving device, display device and driving method are provided. The shift register unit includes: an input circuit, configured to control a potential of a pull-up control node based on an input signal; a pull-down control circuit, configured to control a potential of a pull-down control node based on the input signal and the potential of the pull-up control node when first signal is at a first level; a pull-down circuit, configured to pull down the potential of the pull-up control node based on the potential of the pull-down control node; a pull-up circuit, configured to control an output signal output from a signal output terminal based on the potential of the pull-up control node and the clock signal; and a reset circuit, configured to reset the output signal based on the potential of the pull-down control node when second signal is at a second level.

Shift register unit, gate driving device, display device and driving method

An array substrate, a manufacturing method of the array substrate and a display device including the array substrate are disclosed. The array substrate includes a substrate (), a common electrode layer () located on the substrate () and a conductive layer () provided on a surface of the substrate (), the conductive layer () and the common electrode layer () are electrically connected in parallel. The common electrode and the conductive layer are formed into a parallel structure, so that the resistance can be decreased, and in turn, crosstalk, greenish and other phenomenon of the array substrate are reduced, thereby promoting the picture quality of the display device.

Array substrate and manufacturing method thereof, display device

A shift register unit and a control method thereof, a gate drive device including the shift register unit, and a display device. The shift register unit includes: an input module, a pull-up module, a first pull-down control signal generation module, controlling, in the period that a first signal is high level, potential of a first pull-down control node according to a drive input signal and potential of a pull-up control node; a second pull-down control signal generation module, controlling, in the period that a second signal is high level, potential of a second pull-down control node according to the drive input signal and the potential of the pull-up control node, the first signal and the second signal alternatively becoming high level; and a pull-down module, pulling down a drive output signal according to the potential of the first pull-down control node and the potential of the second pull-down control node.

Shift register unit, gate drive device, display device, and control method

A circuit and method for testing transistor(s) are provided. The circuit is used for testing a set of transistors including at least two transistors, and the circuit includes: a first power supply voltage terminal connected to first electrodes of the respective transistors; a first control signal terminal connected to control electrodes of the respective transistors; and a set of test terminals including at least two test terminals; the test terminals are connected to second electrodes of the corresponding transistors, respectively.

Circuit and method for testing transistor(s)

There is provided a gate driving circuit and driving method thereof, and display apparatus. The method comprises: performing gate drive scanning on shift register units located in a first region in the gate driving circuit; performing touch scanning after the gate drive scanning of the shift register units in the first region is completed; scanning again a last stage of shift register unit located in the first region before the touch scanning is completed, so that the last stage of shift register unit located in the first region pre-charges a first stage of shift register unit located in a second region; and performing gate drive scanning on shift register units located in the second region in the gate driving circuit, the last stage of shift register unit located in the first region connected in cascades with the first stage of shift register unit located in the second region.

Gate driving circuit and driving method thereof, and display apparatus

A data driving circuit comprises a plurality of driving units, each of the driving units comprising first, second, third and fourth switch units, each of the switch units comprising first and second input terminals and an output terminal; the output terminals being output terminals of the data driving circuit; two data control terminals, one of which is respectively connected to the first input terminals of the first switch unit and the second switch unit, the other of which is respectively connected to the first input terminals of the third switch unit and the fourth switch unit; a first switching control terminal, connected to the second input terminal of one of the switch units connected to the same data control terminal; a second switching control terminal, connected to the second input terminal of the other of the switch units connected to the same data control terminal.

Growing community of inventors

Beijing, China

Seung Woo Han