Samsung Electronics Co., Ltd.

Seung-whan Seo

Hyun-Soon Jang

Kwun-soo Cheon

Jae-sung Kang

Byung-heon Kwak

Sang-Joon Ryu

Yong-hwan Cho

Hyun-tae Lim

A parallel bit test (PBT) apparatus, included in memory chips that are stacked in a multi-chip package (MCP) and that share a set of data signal lines, may include: a comparing unit to output a data signal representative of a comparison between test data signals provided to a given one of the memory chips and corresponding data signals output therefrom, respectively; and a coding unit to output the representative data signal using a first subset of the shared set of data signal lines, the first subset not overlapping other subsets used by coding units corresponding to the other ones of the memory chips, respectively, the coding unit selecting one or more of the data signal lines amongst the shared set of data signal lines for inclusion in the first subset according to a first test mode register set (MRS) signal.

Parallel bit test apparatus and parallel bit test method capable of reducing test time

Provided are a semiconductor memory device having a post package repair control circuit and a post package repair method. In the semiconductor memory device and the post package repair method, in a post package repair mode, a second memory bank is used as a fail bit map memory for storing failed bit information regarding a first memory bank, and the first memory bank is used as a fail bit map memory for storing failed bit information regarding the second memory bank.

Semiconductor memory device including post package repair control circuit and post package repair method

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Cheonan-si, South Korea

Seung-whan Seo