Samsung Electronics Co., Ltd.

Seung Weon Paek

Jae Hwan Kim

Byung Chul Shin

Jae Hyun Kang

Byung-Moo Kim

Ki Heung Park

Methods of fabricating semiconductor devices are provided. A method of fabricating a semiconductor device includes selecting a target pattern from a target design layout. The target pattern includes: a target net; a target via that is electrically connected to the target net; and a crossing net that is electrically connected to the target via on a different level from the target net. The method includes analyzing a peripheral pattern that is adjacent the target net. Moreover, the method includes generating a redundant net, and a redundant via that electrically connects the redundant net and the crossing net. Related layout design systems are also provided.

Methods of fabricating semiconductor devices, and related layout design systems

A method of designing a layout of a semiconductor device includes preparing a layout for a semiconductor integrated circuit, the preparing of the layout including providing lower and upper metal patterns and via patterns, which are vertically interposed between the lower and upper metal patterns, performing a retargeting process on the lower and upper metal patterns, classifying the via patterns to extract at least one risk via from the via patterns and changing a position of the risk via. During the changing of the position of the risk via, all of the via patterns, other than the risk via, are unchanged in position thereof. Related systems and computer program products are disclosed.

Growing community of inventors

Yongin-si, South Korea

Seung Weon Paek