Korea Advanced Institute of Science and Technology

Samsung Electronics Co., Ltd.

Obsidian Sensors, Inc.

Samsung Display Co., Ltd.

Korea Electronics Technology Institute

Seung-Tak Ryu

John Hyunchul Hong

Bing Wen

Tallis Young Chang

Edward Chan

Miyoung Kim

Michael Choi

Keumdong Jung

Sang-Gug Lee

Kwang Ho Ahn

KyungTea Park

Ohjo Kwon

Sang-Hyun Cho

Barosaim Sung

Jaekeun Lee

Ki-Jin Kim

Hyungjong Ko

Minjae Seo

Seungyeob Baek

Ilhoon Jang

Jong-In Kim

Yeong-Shin Jang

Jae-Hyun Chung

Kun-Woo Park

Min-Jae Seo

Dongjin Chang

Methods of sensor readout and calibration and circuits for performing the methods are disclosed. In some embodiments, the methods include driving an active sensor at a voltage. In some embodiments, the methods include use of a calibration sensor, and the circuits include the calibration sensor. In some embodiments, the methods include use of a calibration current source and circuits include the calibration current source. In some embodiments, a sensor circuit includes a Sigma-Delta ADC. In some embodiments, a column of sensors is readout using first and second readout circuits during a same row time.

Readout circuits and methods

An analog-to-digital converter includes: a sample/hold circuit, which samples an analog signal, and outputs a first voltage; a digital-to-analog conversion circuit, which converts a digital signal to output a second voltage; an amplifier, which amplifies the first voltage and the second voltage; a noise shaping filter, which integrates a residual voltage corresponding to a difference between the amplified first voltage and the amplified second voltage, and generates a first integration voltage and a second integration voltage; a comparator, which compares a sum of the amplified first voltage, the first integration voltage, and the second integration voltage with the amplified second voltage; and a SAR logic, which outputs the digital signal according to a comparison result of the comparator, and controls the digital-to-analog conversion circuit.

Analog-to-digital converter, method of analog-to-digital conversion, and electronic apparatus

An electronic circuit includes a first converting circuit, an amplifying circuit, and a second converting circuit. The first converting circuit outputs a first residual voltage associated with converting an analog signal into a first digital signal and a second residual voltage generated based on the first residual voltage. The amplifying circuit generates a third residual voltage by amplifying the first residual voltage through an amplifying path during a first time duration and generates a fourth residual voltage by amplifying the second residual voltage through the amplifying path during a second time duration after the first time duration. The second converting circuit generates a second digital signal associated with the analog signal by performing an interpolation operation based on the third residual voltage and the fourth residual voltage.

Electronic circuit including pipeline converting circuit

An electronic circuit includes an analog to digital converter (ADC) and a noise coupling filter. The ADC generates a digital output signal based on a first analog signal and a second analog signal. The noise coupling filter generates the second analog signal to be fed back for an input to the ADC, based on a first quantization error signal associated with converting the first analog signal to the digital output signal. The noise coupling filter performs noise shaping on a digital error signal derived from the quantization error signal and generates the second analog signal from a result of the noise shaping, using a clock in the digital domain.

Electronic circuit for implementing modulator configured to perform noise shaping in digital domain

An electronic circuit includes a reference ADC, a delay circuit, and a main ADC. The reference ADC converts an input signal to an upper bit string of output data, in response to a reference clock. The delay circuit delays a source clock by a delay time to output a main clock. The main ADC converts the input signal to a lower bit string of the output data, in response to the main clock. When a value of the most significant bit included in the lower bit string is identical to a value of the bit which is adjacent to the most significant bit and lower than the most significant bit, the delay time is adjusted based on a direction in which a level of the input signal is changed and the value of the most significant bit of the lower bit string.

Electronic circuit adjusting timing of clock based on bits of output data from sub-ranging analog-to-digital converter

An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique.

Analog-to-digital converter

A digital feedforward sigma-delta modulator in an analog-to-digital converter and its modulation method are disclosed. The modulator changes a feedforward path from an analog domain to a digital domain and processes it. The modulator integrates an analog input by using a plurality of integrators, weights them, quantizes them by using a plurality of quantizers in a digital domain to output digital signals, and then adds up the thusly outputted digital signals by using a digital adder. In case of a continuous time digital feedforward sigma-delta modulator (SDM), a digital signal outputted from the digital adder is weighted and then immediately inputted to the digital adder in the digital domain so as to be subtracted, allowing for digital feedforwarding. Because the feedforward signal is processed in the digital domain, the area occupied by an analog circuit and power consumption can be reduced. Also, because signals are added up in the digital domain, a digital output signal can be immediately used when an excess loop delay needs to be corrected. Thus, because there is no need to convert the digital output signal into an analog signal by using a DAC, the DAC can be omitted.

Digital feedforward sigma-delta modulator in analog-to-digital converter and modulation method thereof

An apparatus for digital error correction in a successive approximation (SAR) analog to digital converter (ADC) includes a binary weighted digital to analog converter (DAC) which can be virtually divided into multiple sub-DACs for redundancy insertion; and a comparator configured to compare the analog input with a DAC level corresponding to digital. The apparatus further includes a register and control logic unit configured to control a switching operation for DAC and to add output codes obtained from sub-DACs to output the added code as a final A/D converted code.

Method and apparatus for digital error correction for binary successive approximation ADC

An electronic circuit includes a digital-to-analog converter (DAC), and an active integrator. The DAC converts a digital output of the electronic circuit to an analog signal and feeds back the analog signal. The active integrator includes an operational amplifier having a first input terminal that receives a summed signal of an input signal and the fed back analog signal, and a second input terminal that receives a reference voltage. The DAC includes a coupling capacitor, first switches, at least one current source, second switches, and a third switch.

Continuous time delta-sigma modulator and electronic circuit including the same

A pipelined analog-to-digital converter (ADC) has a multistage structure, and the pipelined ADC includes a plurality of stages that form the multistage structure. Each of the stages includes a sample-and-hold (S/H) circuit, a flash ADC, and a digital-to-analog converter (DAC). The S/H circuit converts an analog input signal to a digital signal. The flash ADC detects a digital bit corresponding to the analog input signal. The DAC converts the digital signal to an analog signal, and amplifies a residue signal, which is a difference between the input analog signal and the converted analog signal, that is provided as an analog input signal of the next stage.

Pipelined analog-to-digital converter and method of analog-to-digital conversion

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Daejeon, South Korea

Seung-Tak Ryu