University of California

International Business Machines Corporation

University of Illinois

Seung-Moon Yoo

Sung-Mo Kang

Gary Dale Carpenter

Kevin John Nowka

Juan-Antonio Carballo

Ivan Vo

Jeffrey L Burns

A level shifter circuit is disclosed. The circuit receives a digital input signal characterized by a logical high state having a first high voltage level and generates an output node for driving a digital output signal characterized by a logical high state having a second high voltage level. The output signal logical state mirrors the input signal logical state. The circuit includes a short circuit current reduction mechanism for charging a first internal node of level shifter circuit following a first transition of the input signal logical state. The circuit further includes a performance enhancement mechanism for discharging the first internal node of the level shifter circuit following a second transition of the input signal logical state. The performance enhancement mechanism may comprise a transistor driven by the input signal and connected between the first internal node and ground. The current limiting mechanism may comprise a transistor having a source/drain terminal connected to the first internal node.

Level shifter circuit

An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and to a gate of the second PMOS transistor; and an output switch coupled to controllably communicate a stored data value from the storage node to the output node.

Self reverse bias low-power high-performance storage circuitry and related methods

A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Method of transparently reducing power consumption of a high-speed communication link

An integrated circuit is provided which includes a multi-state circuit with a first PMOS transistor and a first NMOS transistor. In an active mode, the multi-state circuit is operable to switch between a first state in which the first PMOS transistor is turned on and the first NMOS transistor is turned off and a second state in which the first PMOS transistor is turned off and the first NMOS transistor is turned on. A power source NMOS transistor has a drain connected to a supply voltage terminal and has a source connected to a source of the first PMOS transistor. A power source PMOS transistor has a drain connected to a an effective ground terminal and has a source connected to a source of the first NMOS transistor.

Low-power high-performance integrated circuit and related methods

Methods and circuits are described for reducing power consumption within digital logic circuits by blocking the passage of clock signal transitions to the logic circuits when the clock signal would not produce a desired change of state within the logic circuit, such as at inputs, intermediary nodes, outputs, or combinations. By way of example, the incoming clock is blocked if a given set of logic inputs will not result in an output change of state if a clock signal transition were to be received. By way of further example, the incoming clock is blocked in a data flip-flop if the input signal matches the output signal, such that receipt of a clock transition would not produce a desired change of state in the latched output. The invention may be utilized for creating lower power combinatorial and/or sequential logic circuit stages subject to less unproductive charging and discharging of gate capacitances.

Event driven dynamic logic for reducing power consumption

Methods, and arrangements to enhance speed and reduce power consumption in a scanable latch circuit are disclosed. Embodiments include a wired-or circuit to facilitate independent paths for scan data and normal input data through the scanable latch circuit. In particular, to reduce delays related to gates between the input pin for the system clock and a normal input gate, dual, substantially independent paths are implemented: a scan path and a normal input path. Embodiments coordinate transmission of data from a normal input gate and a scan input gate to an output latch, a scan out pin, and/or combinational logic by incorporating buffers that isolate a wired-or node from either the scan input gate, the normal input gate, or both with a high impedance.

Methods and arrangements for an enhanced scanable latch circuit

An integrated circuit is provided comprising a latch circuit including, a first inverter including a first high threshold voltage PMOS transistor and a first high threshold voltage NMOS transistor with a first data node comprising interconnected source/drains (S/D) of the first PMOS and NMOS transistors; a second inverter including a second high threshold voltage PMOS transistor and a second high threshold voltage NMOS transistor with a second data node comprising interconnected source/drains (S/D) of the second PMOS and NMOS transistors; wherein the gates of the first PMOS and first NMOS transistors are coupled to the second data node; wherein the gates of the second PMOS and second NMOS transistors are coupled to the first data node; a first low threshold voltage access transistor including a first S/D coupled to the first data node and to the gate of the second PMOS transistor and to the gate of the second NMOS transistor and including a second S/D coupled to a first data access node and including a gate coupled to a first access control node; and a second low threshold voltage access transistor including a first S/D coupled to the second data node and to the gate of the first PMOS transistor and to the gate of the first NMOS transistor and including a second S/D coupled to a second data access node and including a gate coupled to a second access control node.

Low-power high-performance storage circuitry

Methods and arrangements for enhancing domino logic are disclosed. Embodiments include a keeper circuit to pull up a domino node in response an output of an output circuit when the domino node is at a high voltage and to stop pulling up the domino node before the output changes to a first logical output. Further embodiments include an accelerator circuit to pull down the domino node when the keeper circuit stops pulling up the domino node. The domino node may couple with a pre-charge circuit and be pre-charged to a high voltage during a first portion of a clock cycle. The domino node may also couple with a logic input circuit to pull down the domino node during a second portion of the clock cycle, causing the output circuit to change the output from low to high in response to logic signals.

Methods and arrangements for enhancing domino logic

A flip-flop circuit that includes a set of three p-channel connectors connected in parallel between a supply voltage (Vdd) and a first control node. The circuit further includes three n-channel transistors connected in series between the first control node and Vss. The first control node controls the gate of a p-channel transistor connected between Vdd and an output node. A set of n-channel transistors is connected between the output node and ground. The gates of these transistors are controlled by the clock signal, a delayed clock signal, and an inverted copy of the data signal, which is provided, via a control inverter, to a second control node. The first control node drives the output node to a first state and the second control node drives the output node to a second state. The first and second control nodes are preferably decoupled.

Flip-flop circuit for use in electronic devices

A reverse biasing logic circuit is disclosed for limiting standby leakage electric current losses during circuit operation. The circuit includes a logic function circuit having one or more logic transistors that receive an input and perform a logic function operation to generate an output. A power source transistor connects to the logic function circuit and receives a control signal that changes node voltages of the one or more logic transistors between an active mode and a standby mode. During the standby mode, the power source transistor causes reverse biasing of at least one of the one or more logic transistors which prevents a leakage electric current flow between the power source transistor and the one or more logic transistors.

Growing community of inventors

Austin, TX, United States of America

Seung-Moon Yoo