International Business Machines Corporation

Zmos Technology, Inc.

Seung-moon Yoo

Kevin John Nowka

Juan-Antonio Carballo

Ivan Vo

Myung Chan Choi

Sang-Kyun Han

Sung Ju Son

Young Tae Kim

Hung Cai Ngo

Sun Hyoung Lee

Jeongduk Sohn

Oh Sang Yoon

Jae Hoon Yoo

A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Digital transmission circuit and interface providing selectable power consumption via multiple weighted driver slices

Circuits and methods for suppressing integrated circuit leakage currents are described. Many of these circuits and methods are particularly well-suited for use in dynamic memory circuits. Examples describe the use of power, ground, or both and power and ground source transistors used for generating virtual voltages. An aspect of the invention describes lowering refresh current. An aspect describes reducing the standby current. An aspect of the invention describes lowering leakage resulting from duplicated circuits, such as row decoders and word line drivers. An aspect describes methods of performing early wake-up of source transistors. A number of source transistor control mechanisms are taught. Circuit layouts methods are taught for optimizing integrated circuit layouts using the source transistors.

Low power memory control circuits and methods

Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate drives of these stacked transistors are modulated with different voltage levels in response to the operating power mode of the circuit, for example active mode, active-standby mode, and deep power-down mode. Means for driving these source stacks are described. In one embodiment separate virtual nodes are adapted for different types of circuits, such as buffers, row address strobe, and column address strobe. Other techniques, such as directional placement of the transistors is also described.

Source transistor configurations and control methods

A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices

A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.

Digital transmission circuit and method providing selectable power consumption via single-ended or differential operation

A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.

Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices

A phase detector employs a modified logic gate in conjunction with a set/reset latch to make a phase detector that generates control outputs for use in increasing and decreasing the delay in a delay circuit in the path of a feedback clock generated by delaying a reference clock. The delay circuit provides a controllable delay from less than to greater than one clock cycle of the reference clock. The phase detector generates an up control (UP) signal for increasing delay when the feedback clock leads the reference clock and a down control (DN) signal for decreasing delay when the feedback clock lags the reference clock. The UP signal and DN signal are updated each clock cycle when the leading clock edge makes a transition.

Growing community of inventors

Santa Clara, CA, United States of America

Seung-moon Yoo