Samsung Electronics Co., Ltd.

Seung-mo Ha

Sang-Su Kim

Do-hyoung Kim

Jae-Hwan Lee

Tae-Jong Lee

Dong-hoon Khang

Jung-han Lee

Hwan-Wook Choi

Seung-Jin Mun

Cheol Kyu Kim

Yong-Joon Choi

Myeong-Cheol Kim

Jin-wook Lee

Kwan-heum Lee

Keun-Hee Bai

Woo-Ram Kim

Dong-Seok Lee

Mirco Cantoro

Kwang-Yong Yang

Ki-il Kim

Tae-yong Kwon

Young-Mook Oh

Ah-Young Cheon

Chang-Jae Yang

Woong-ki Hong

So-ra You

Seong-Ju Kim

A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

Semiconductor devices

A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Method of manufacturing semiconductor device having stressor

FinFET semiconductor device with a dummy gate, first gate spacer and second gate spacer

A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.

Method of manufacturing semiconductor device using multiple patterning techniques

Semiconductor device having stressor and method of manufacturing the same

Semiconductor devices and methods of manufacturing the same

An active pattern structure may include a substrate including an active pattern array defined by a plurality of trenches including first to third trenches, and first to third isolation patterns in the first to third trenches, respectively. The active pattern array may include a plurality of first and second active patterns extending in a first direction, and the first to third trenches may be between the first and second active patterns and may include different widths from each other. The active pattern array may include an active pattern group including one of the first active patterns and one of the second active patterns sequentially arranged in a second direction substantially perpendicular to the first direction. Each of the first and second active patterns may have a minute width.

Active pattern structure and semiconductor device including the same

Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.

Methods for fabricating semiconductor device

A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.

Semiconductor device

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Seoul, South Korea

Seung-mo Ha