Samsung Electronics Co., Ltd.

Seung-Man Shin

Seung-Jin Seo

You-Keun Han

Byung-Se So

Young-Man Ahn

Jung-Kuk Lee

Hyun-Sung Shin

In-Su Choi

Hui-chong Shin

Sang-Joon Hwang

Jong-Geon Lee

Kee-Hoon Lee

Kyung-Hee Han

Ho-Suk Lee

Jong-Cheol Seo

Jung-Ho Jung

A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

Semiconductor memory device and computer system including the same

A semiconductor memory device includes an internal address generating circuit; an internal command generating circuit; and a memory cell array including one or more memory bank groups. The semiconductor memory device is configured such that when a read command or a write command is input, if a first portion of a plurality of memory banks of a first memory bank group from among one or more memory bank groups of the memory cell array performs a read operation or a write operation, a second portion of the plurality of memory banks of the first memory bank group performs a refresh operation.

Semiconductor memory device capable of performing refresh operation without auto refresh command

Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

Method of testing a memory module and hub of the memory module

A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.

Memory module, memory unit, and hub with non-periodic clock and methods of using the same

A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.

Memory module test system for memory module including hub

Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.

Methods and apparatus for interfacing between test system and memory

A memory module testing apparatus and method include a test slot adapted to receive a target memory module, wherein the target memory module includes a first memory unit to store information related to the target memory module. The memory module testing apparatus further includes a second memory unit adapted to store information related to a memory module, and a first switching unit adapted to selectively provide a driving signal to at least one of the first memory unit and the second memory unit.

Memory module testing apparatus and method of testing memory modules

A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.

A hub for testing memory and methods thereof. The hub may include a test block a test block and a transparent mode block. The test block may be configured to generate a pseudo random pattern based on received memory control information and to write the pseudo random pattern to at least one of a plurality of memory devices in the first operating mode. The transparent mode block may be configured to receive the generated pseudo random pattern from the test block, to read the pseudo random pattern from the at least one of the plurality of memory devices in the first operating mode and to compare the generated pseudo random pattern with the read pseudo random pattern. Also, the hub may perform a transparent mode test on at least one memory device of a memory module with a pseudo random data pattern, the pseudo random data pattern based at least in part on memory control information received from a device not included within the memory module.

Hub for testing memory and methods thereof

A test board for a high-frequency system level test: The test board includes a main board having through holes filled with a conductive material. These holes may be located at a portion of the main board from which an existing module socket has been removed. An interface board has surface mounted device (SMD) pads on front and rear surfaces. The SMD pads on the front surface of the interface board are connected with the SMD pads on the rear surface thereof through cross connection wiring within the interface board for a pin swap. The through holes of the main board are connected with the SMD pads on the rear surface of the interface board via iron cores fixed at a guide. A test module socket is mounted on surfaces of the SMD pads on the front surface of the interface board.

Growing community of inventors

Suwon-si, South Korea

Seung-Man Shin