Samsung Electronics Co., Ltd.

Cheil Industries Inc.

Samsung Corning Precision Materials Co., Ltd.

Samung Electronics Co., Ltd

Seung-man Choi

Bong-Seok Suh

Young Oh

Hong-Jae Shin

Hong-shik Shim

Hyun-Min Kim

Eun-young Cho

You-min Shin

Gil-heyun Choi

Kyoung-woo Lee

Ki-Chul Park

Chul-Ho Jeong

Hyo-Jong Lee

Sang-bum Kang

Il-Ryong Kim

Young-hyun Ju

Yoon-Hae Kim

Ja-hum Ku

Soo-geun Lee

Sun-Jung Lee

Jeong-Hoon Ahn

Young-jin Wee

Andrew-Tae Kim

Byung-jun Oh

Chul-ho Jeong

Provided is a color improving film comprising a base layer, a high refractive light diffusion layer including an organic light diffuser on the base layer, a high refractive resin layer on the high refractive light diffusion layer, and a low refractive resin layer in which a lenticular lens pattern is formed on the high refractive resin layer, wherein the organic light diffuser comprises particles coated with a black pigment and non-coated particles, and wherein the lenticular lens pattern is formed on a surface of the low refractive resin layer facing the high refractive resin layer. According to the color improving film, a change in color sensitivity according to an angle of view is small, an external light reflectivity is low, and a light transmittivity and a light diffusibility are substantially improved. Also, the method of preparing the color improving film has excellent processiblity and economic efficiency.

Color improving film and method of manufacturing the same

Provided are a color display film, a method for manufacturing the same, and a display apparatus including the color display film. The color display film includes a base material layer, a high-refractive light diffusion layer including a light diffuser, a high-refractive resin layer, and a low-refractive resin layer on which an optical pattern is formed. The method for manufacturing a color display film includes forming a high-refractive light diffusion layer by coating a resin comprising a diffuser on one surface of a base material layer and hardening the resin, forming a high-refractive resin layer, in which optical patterns are formed, on one surface of the high-refractive light diffusion layer, and forming a low-refractive resin layer having optical patterns formed on one surface thereof by coating a low-refractive transparent resin on a surface of the high-refractive resin layer in which the optical patterns are formed and hardening the resin.

Film for improving color display and method for manufacturing the same, and display apparatus including improved color display film

Provided are a color display film and a method for manufacturing the same, and a display apparatus. The color display film includes a base material layer, a high-refractive resin layer on which an optical pattern is formed, and a low-refractive light diffusion layer including a light diffuser in a stacked configuration. The optical pattern is formed in one surface of the high-refractive resin layer facing the low-refractive light diffusion layer. The method of manufacturing a color display film includes forming a high-refractive resin layer by coating a high-refractive transparent resin on one surface of a base material layer and forming an imprinted optical pattern on the coated high-refractive transparent resin, forming a low-refractive light diffusion layer by dispersing a light diffuser into a low-refractive transparent resin, and bonding one surface of the low-refractive light diffusion layer on a surface on which the optical pattern is formed.

Film for improving color display and method of manufacturing the same

A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities

A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method

In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Semiconductor device and method of manufacturing the same

Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.

In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.

Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby

In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.

Metal-insulator-metal (MIM) capacitor and method of fabricating the same

Methods of forming a metal layer in integrated circuit devices using selective electroplating in a recess are disclosed. In particular, a recess is formed in a surface of an insulating layer. The recess has a side wall inside the recess, a bottom inside the recess, and an edge at a boundary of the surface of the insulating layer and the side wall. A selective electroplating mask is formed on the side wall to provide a covered portion of the side wall and an exposed portion of the side wall. The exposed portion of the side wall can be electroplated with a metal. Related conductive contacts are also disclosed.

Growing community of inventors

Hwaseong-si, South Korea

Seung-man Choi