Other

Pt Plus Co., Ltd.

Snu Rdb Foundation

Neopoly Inc.

Seung Kee Joo

Seung Ki Joo

Seok Woon Lee

Seok-Woon Lee

Jang Sik Lee

Ki Bum Kim

Young Su Kim

Yeo Geon Yoon

Hyeong Suk Yoo

Yong Woo Lee

Se Wan Son

Chang Wook Jeong

Woo Chang Lim

Eung Chul Park

Hyun Mo Kang

Chang Woo Byun

Sang Joo Lee

Seol Ah Park

Tao Li

Seung Jae Yun

Nam Kyu Song

Provided is a method of crystallizing an amorphous silicon thin film transistor and a method of fabricating a polycrystalline thin film transistor using the same, in which the polycrystalline thin film transistor indicating leakage current characteristics of a level that is applicable for active matrix organic light emitting diode displays (AMOLEDs) can be manufactured by using a silicide seed induced lateral crystallization (SILC) method. The amorphous silicon thin film transistor crystallizing method includes the steps of: forming an amorphous silicon layer on a substrate; forming an active region by patterning the amorphous silicon layer; forming a crystallization induced metal layer in both a source region and a drain region that are placed on both side ends of the active region; forming a number of dot-shaped metal silicide seeds on the surfaces of the source region and the drain region made of amorphous silicon by removing the crystallization induced metal layer; and crystallizing the active region formed of the amorphous silicon layer by heat-treating the substrate by using the metal silicide seeds as crystallization seeds.

Method for crystallizing amorphous silicon thin film and method for fabricating poly crystalline thin film transistor using the same

Provided is a polysilicon thin film transistor having a trench type bottom gate structure using copper and a method of making the same. The polysilicon thin film transistor includes: a transparent insulation substrate; a seed pattern that is formed in a pattern corresponding to that of a gate electrode on the transparent insulation substrate, and that is used to form the gate electrode; a trench type guide portion having a trench type contact window in which an upper portion of the seed pattern is exposed; the gate electrode that is formed by electrodepositing copper on a trench of the exposed seed pattern; a gate insulation film formed on the upper portions of the gate electrode and the trench type guide portion, respectively; and a polysilicon layer in which a channel region, a source region and a drain region are formed on the upper portion of the gate insulation film.

Polysilicon thin film transistor having trench type copper bottom gate structure and method of making the same

Disclosed herein is a polycrystalline silicon solar cell, including: a back electrode formed on a transparent insulating substrate; an N-type polycrystalline silicon layer in which amorphous silicon is crystallized through MIC process, and in which electrons are accumulated; a light-absorbing layer which is formed by vertically crystallizing an intrinsic amorphous silicon layer using the polycrystalline silicon layer as a seed for crystallization through MIVC process, in which pairs of electrons and holes are generated in response to incident light, and which has a vertical column grain structure in which grains are arranged in the direction in which electrons and holes move; a P-type polycrystalline silicon layer which has the vertical column grain structure, and in which holes are accumulated; a transparent electrode layer; front electrodes; and an antireflection coating film, and is a method of fabricating the same.

Polycrystalline silicon solar cell having high efficiency and method for fabricating the same

Disclosed herein is a method of forming a light-absorbing layer of a polycrystalline silicon solar cell, including: forming a polycrystalline silicon layer on a back electrode; forming an intrinsic amorphous silicon layer on the polycrystalline silicon layer; and heat-treating the transparent insulating substrate to vertically crystallize the intrinsic amorphous silicon layer using the polycrystalline silicon layer as a seed for crystallization through a metal induced vertical crystallization (MIVC) process to form the intrinsic amorphous silicon layer into a light-absorbing layer made of polycrystalline silicon, and is a method of fabricating a high-efficiency polycrystalline silicon solar cell using the light-absorbing layer.

A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.

Poly-silicon thin film transistor having back bias effects and fabrication method thereof

The present invention relates to a structure and a fabrication method of a storage capacitor used in the pixel region of a display panel such as LCD or OELD. The present invention simultaneously forms a poly-crystalline silicon TFT and a storage capacitor in the pixel region of a display panel using MILC phenomena. By applying MILC inducing metal along at least two edges of storage capacitor, the time required to crystallize the silicon layer in storage capacitor region may be significantly reduced.

Storage capacitor structure for LCD and OELD panels

The present invention relates to a method for crystallizing the active layer of a thin film transistor utilizing crystal filtering technique. According to the conventional metal induced lateral crystallization (MILC) method, amorphous silicon layer can be crystallized into poly-crystal silicon layer. According the crystal filtering technique of the present invention, amorphous silicon layer can be single-crystallized by filtering a single crystal component from the poly-crystal region being crystallized by MILC. The TFT fabricated including an active layer crystallized according to the present method has significantly improved electrical characteristics such as electron mobility and leakage current as compared to the TFT including a poly-crystal silicon active layer made by conventional methods. The invention also provides various TFT fabrication methods applying the crystal filtering technique.

Method for crystallizing a silicon layer and fabricating a TFT using the same

Method for crystallizing silicon layer

Disclosed is a process for depositing an aluminum oxide thin film necessary for semiconductor devices. The process includes the steps of: subjecting a gaseous organoaluminum compound as an aluminum source in contact with a target substrate and depositing aluminum using plasma. The steps are sequentially repeated to form an aluminum thin film, and further includes the step of oxidizing the aluminum thin film using oxygen plasma. This deposition cycle is repeated to obtain an aluminum oxide thin film. The present invention uses an aluminum source containing less contaminant compared to the prior art, thus obtaining aluminum oxide of high quality. Furthermore, the temperature of the gas supply and the reactor can be lowered in relation to the prior art method to reduce costs in the fabrication of semiconductor devices.

Process for forming aluminum or aluminum oxide thin film on substrates

A thin film transistor (TFT) including a polycrystalline active layer and a method for making the same are disclosed. An amorphous silicon layer is deposited on a substrate and is crystallized by using MJLC (metal induced lateral crystallization) to provide a poly-silicon active layer of the TFT. Specifically, the amorphous silicon layer is poly-crystallized during a thermal treatment of the active layer. The thermal treatment causes the MILC of the active layer propagating from portions of the source and the drain regions on which MILC source metal is formed through the contact holes of the TFT.

Thin film transistor including polycrystalline active layer and method for fabricating the same

The invention provides a method for fabricating a TFT including a crystalline silicon active layer. The inventive method forms a metal offset region between the metal layer used to induce the cystallization of the active layer and the channel region of the TFT without introducing an additional process such as photoresist processing. Therefore, the inventive method improves the performance and manufacturing productivity of TFT and lower its production cost as well.

Method for fabricating thin film transistor including crystalline silicon active layer

A method for fabricating a TFT including a crystalline silicon active layer is disclosed, in which the metal which induced the crystallization of the active layer is offset from a gate electrode utilizing a mask used to form a lightly doped drain (LDD) region or an offset junction region in the active layer. The TFT includes a silicon active layer crystallized by crystallization inducing metal and a gate electrode, and has an LDD region or an offset junction region formed in the vicinity of the channel region. The method for fabricating the TFT forms a metal offset region without using an additional photoresist forming process, and forms a LDD region by conducting a low density doping in the metal offset region. As a result, a transistor made according to the present invention has low leakage current in its off-state, and has stable electrical characteristics in its on-state.

A method for fabricating a large single-grained ferroelectric thin film grown by selectively nucleated lateral crystallization (SNLC) using an artificial nucleation seed, a method for fabricating a ferroelectric capacitor using the same, and a method for fabricating a ferroelectric memory device using the same. The ferroelectric thin film fabrication method includes the steps of forming a first conductive layer on one side of a semiconductor substrate, by using a conductive material, forming an artificial nucleation seed in an island form adjacent a position where a ferroelectric thin film is to be formed in the upper portion of the first conductive layer, forming a ferroelectric thin film on the whole surface of the substrate including the nucleation seed, and thermally annealing the ferroelectric thin film to thereby grow the ferroelectric thin film positioned in the lateral side of the nucleation seed into a single-grained ferroelectric thin film.

Methods for fabricating large single-grained ferroelectric thin film, for fabricating ferroelectric thin film capacitor using the same, and for fabricating ferroelectric memory device using the same

A method for fabricating a ferroelectric thin film, capable of preventing degradation due to fatigue and aging of a ferroelectric thin film of PZT and enabling crystallization at a low temperature. The ferroelectric thin film fabrication method includes the steps of forming an insulation layer on one side of a semiconductor substrate, forming an electrode layer on the insulation layer, forming a ferroelectric layer on the electrode layer, and performing an ion damage processing on the ferroelectric layer using an ionized gas.

Growing community of inventors

Seoul, South Korea

Seung Ki Joo