Samsung Electronics Co., Ltd.

Other

Seung-Keun Lee

Byeong-Hoon Lee

Young-Ho Lim

Jin-Sung Park

Seung-Won Lee

Dong-Ho Park

Choong-keun Kwak

Pyung-Moon Zhang

Chang-Hyun Lee

Sang-Wan Nam

Choong-Keun Kwak

Dae-Seok Byeon

Ji-Ho Cho

Tae-Sung Jung

Ki-Hwan Choi

Bo-Geun Kim

Sang-Pil Sim

Dae-Han Kim

Myong-Jae Kim

Hwi-Taek Chung

Byeng-Sun Choi

Kang-Deog Suh

Chang-Rae Kim

Dong-Gi Lee

Yun-Heub Song

Doo-Sub Lee

Hong-soo Jeon

Joon-Sung Lee

Chan-Jo Lee

Ga-pyo Nam

Jin-Seon Yeom

San-Hong Kim

Myoung-Jae Kim

Doo-Seop Lee

Myung-Jae Kim

The NOR flash memory device according to the present invention is operated by a high voltage supplied from bitline selection transistors and includes a bitline bias circuit for supplying a bias voltage of a constant level to the bitline bias transistor. In accordance with the present invention, it is possible to stably supply a desired voltage closing to a power voltage to the bitline bias transistor.

Bitline bias circuit and nor flash memory device including the bitline bias circuit

Disclosed is a charge pump circuit that operates responsive to a test or general operation mode. The charge pump circuit includes at least one charge pump part. A voltage level sensing block generates a level sensing signal by sensing an output voltage. An oscillator generates complementary pulse signals responsive to the level sensing signal. And a selecting circuit block generates a selected voltage that is one of a high voltage and a supply voltage to the at least one charge pump part, the high voltage having a level higher than the supply voltage.

Charge pump circuit operating responsive to a mode

A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage generating unit for generating a negative voltage through a first charge pump; and a second voltage generating unit for generating a positive voltage through a second charge pump. During an accelerated programming operation, the first voltage generating unit increases a pumping efficiency of the first charge pump using an external power supply voltage, and the second voltage generating unit directly outputs the external power supply voltage.

Nonvolatile semiconductor memory device and voltage generating circuit for the same

A flash memory device that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with the selected columns by the column selector circuit. The column selector circuit variably selects the columns according to whether the column address is 4N-aligned (where N is an integer having a value of 1 or more). For example, the column selector circuit chooses columns of the column address when the column address is 4N-aligned, and chooses columns of an upper column address when the column address is not 4N-aligned.

Flash memory device with burst read mode of operation

A NOR flash memory device comprises a memory cell adapted to store at least two bits of data. A read operation is performed on the memory cell by generating a reference current with a first magnitude to detect the value of a most significant bit (MSB) and generating the reference current with a second magnitude to detect the value of a least significant bit (LSB). The respective values of the MSB and the LSB are detected by comparing the first and second reference currents to an amount of current flowing through the memory cell during the read operation. The respective magnitudes of the first and second reference currents are determined by different reference voltages generated by a reference voltage generator.

Multi-level cell memory device and associated read method

Methods of verifying a program state may be provided for a non-volatile memory device including a multi-bit memory cell transistor providing more than two different program states. More particularly, the multi-bit memory cell transistor may be programmed from a first program state to a second program state, and a reference memory cell corresponding to the second program state may be selected. After programming the multi-bit memory cell transistor to the second program state and after selecting the reference memory cell corresponding to the second program state, a current flowing through the multi-bit memory cell transistor programmed to the second memory state and a current flowing through the reference memory cell may be compared. Programming the multi-bit memory cell transistor to the second program state may then be verified responsive to comparing the currents flowing through the multi-bit memory cell and the reference memory cell.

Methods of program-verifying a multi-bit nonvolatile memory device and circuit thereof

The invention disclosed herein is a non-volatile memory device. The non-volatile memory device comprises: a first transistor connected between a first voltage and a control node, and controlled by a second voltage; a second transistor connected between the first voltage and the control node, and controlled by a third voltage, and a word line driver for driving a word line in responsive to a voltage of the control node. The second voltage is set to a ground voltage during an erase operation. The third voltage is set to a power voltage during the erase operation.

Row decoder circuit for use in non-volatile memory device

Flash memory integrated circuit devices include an integrated circuit substrate. A cell array on the integrated circuit substrate includes a plurality of cell transistors. A bit line is coupled to ones of the plurality of cell transistors and a first pass transistor is coupled to the bit line. The first pass transistor has a first diffusion structure configured to provide a breakdown voltage higher than that of a second diffusion structure. One or more second pass transistor(s) are coupled to the first pass transistor. The second pass transistor(s) have the second diffusion structure. The second diffusion structure may have a resistance smaller than a resistance of the first diffusion structure.

Flash memory devices including a pass transistor

A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.

Memory devices using tri-state buffers to discharge data lines, and methods of operating same

A memory device in accordance with embodiments of the present invention includes a reference cell array and a plurality of banks. Each of the banks includes memory cells. A plurality of current copier circuits corresponds to the banks, respectively. Each of the current copier circuits copies a reference current flowing through a reference cell array to generate a reference voltage. A plurality of sense blocks correspond to the banks, respectively. Each of the sense blocks includes a plurality of sense amplifiers for sensing data from a corresponding bank in response to the reference voltage from the corresponding current copier circuit. Memory cell lay-out area is reduced, and sense speed is increased.

Non-volatile semiconductor memory device

In the non-volatile semiconductor memory device having a sense amplifier for sensing data stored in a selected memory cell by comparing cell current differences from a reference cell, a current sink unit coupled in parallel with a reference line and a data line are provided. The reference line connects between the reference cell and the sense amplifier, and the data line connects between the selected memory cell and the sense amplifier, where the current sink unit together increases currents of the reference line and the data line. Also, the device includes a sink current control unit having a configuration of a current mirror with the current sink unit, the sink current control unit consisting of a switching unit and being for controlling a sink current of the current sink unit. The device improves data sensing speed and controls sensing current in conformity with the characteristics of a memory cell.

Non-volatile semiconductor memory device having sense amplifier with increased speed

A flash memory device can include a local row decoder circuit that is configured to drive word lines coupled to a bank of a flash memory responsive to separate read and write control signals provided thereto from outside the local row decoder circuit. Multiple local row decoder circuits can, therefore, be controlled by a single global row decoder circuit that provides the separate read and write control signals to each of the local row decoder circuits. By locating the combinatorial logic circuits used for decoding addresses in the global row decoder circuit, rather than in the local row decoder circuits, the local row decoder circuits may have reduced size, thereby allowing further reductions in the size of the flash memory device. For example, in some embodiments according to the invention, a NAND logic circuit used for address decoding is located in the global row decoder circuit, thereby allowing the area allocated to the local row decoder circuit to be reduced. Furthermore, because the may be many local row decoder circuits implemented in the flash memory device, the total size of the flash memory may be reduced.

Read-while-write flash memory devices having local row decoder circuits activated by separate read and write signals

We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.

Multi level flash memory device and program method

A flash memory device is disclosed that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with the selected columns by the column selector circuit. The column selector circuit variably selects the columns according to whether the column address is 4N-aligned (where N is an integer having a value of 1 or more). For example, the column selector circuit chooses columns of the column address when the column address is 4N-aligned, and chooses columns of an upper column address when the column address is not 4N-aligned.

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Gyeonggi-do, South Korea

Seung-Keun Lee