Samsung Electronics Co., Ltd.

Seung-Jun Shin

Tae-Young Oh

Ki-Seok Oh

Hye-Ran Kim

Yeon-Kyu Choi

Bong-Hyun Choi

Jong-Ho Lee

Kwang-il Park

Seung-Jun Lee

Hyong-Ryol Hwang

Ju-seong Hwang

Sung-Min Yim

Ik-Joon Choi

Hoon Sin

Si-Wan Kim

Tae-young Oh

A memory system, including a memory controller and a memory, wherein the memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller mixes a second command with the first command and transmits the mixture of the first command and the second command. The memory changes command latch timing depends on the first or second mode.

Memory device and memory system

A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Memory device having a plurality of low power states

A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.

Dynamic random access memory (DRAM) device and memory controller therefor

Dynamic random access memory (DRAM) device, memory controller therefor, and memory system

A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.

Vertical memory devices

Synchronous dynamic random access memory (SDRAM) device, memory controller therefor, and method of operating same

A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.

A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.

Memory device configured to store and output address in response to internal command

Memory system

A memory device includes a memory cell array, a refresh controller, and control logic. The memory cell array includes a plurality of rows. The refresh controller performs a refresh operation on the plurality of rows. The control logic controls a care operation on a first adjacent region that is most adjacent to a first row based on a number of times the plurality of rows are accessed during a first period. The control logic also controls a care operation on a second adjacent region that is second adjacent to a second row based on a number of times the plurality of rows are accessed during a second period. The first and second periods are different periods.

Memory device performing care operation for disturbed row and operating method thereof

A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank. The refresh controller is configured to control the row selection circuit such that the memory device is operated selectively in an access mode or a self-refresh mode in response to a self-refresh command received from a memory controller, the refresh operation is performed in the access mode in response to an active command received from the memory controller and the refresh operation is performed in the self-refresh mode in response to at least one clock signal.

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Incheon, South Korea

Seung-Jun Shin