Advanced Micro Devices Corporation

Seung-Hyun Rhee

Calvin T Gabriel

Richard J Huang

Amit P Marathe

Hyeon-Seag Kim

Christine Hau-Riege

A method of forming an interlevel dielectric (ILD) layer forms a polymer sacrificial ILD on a substrate. After metallization structures are formed in the polymer sacrificial ILD layer, a low power etch back is performed on the sacrificial ILD layer. Dielectric material is non-conformally deposited as an ILD layer over the substrate and the metallization structures, forming air gaps between some of the metallization structures.

Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set

According to one exemplary embodiment, a test structure for determining electromigration and interlayer dielectric failure comprises a first metal line situated in a metal layer of the test structure. The test structure further comprises a second metal line situated adjacent and substantially parallel to the first metal line, where the second metal line is separated from the first metal line by a first distance, and where the first distance is substantially equal to minimum design rule separation distance. The test structure further comprises an interlayer dielectric layer situated between the first metal line and the second metal line. According to this exemplary embodiment, electromigration failure is determined when a first resistance of the first metal line or a second resistance of the second metal line is greater than a predetermined resistance, and interlayer dielectric failure is determined when a first current is detected between the first and second metal lines.

Growing community of inventors

New York, NY, United States of America

Seung-Hyun Rhee