Samsung Electronics Co., Ltd.

Seung-hyun Oh

Jong-woo Lee

Jae-hoon Lee

Chilun Lo

Barosaim Sung

Thomas Byung-Hak Cho

Jong-mi Lee

Byung-Hak Cho

Woo-jin Jang

Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.

Carrier aggregated signal transmission and reception

A radio frequency (RF) integrated circuit is provided. The RF integrated circuit supports carrier aggregation and includes first receiving circuits and a first shared phase locked loop circuit that provides a first frequency signal of a first frequency to the first receiving circuits. One of the first receiving circuits includes an analog to digital converter (ADC) and a digital conversion circuit. The ADC converts an RF signal received by the one of the first receiving circuits to a digital signal by using the first frequency signal. The digital conversion circuit generates a digital baseband signal by performing frequency down conversion on the digital signal.

Radio frequency integrated circuit supporting carrier aggregation and wireless communication device including the same

Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

Delta modulator with variable feedback gain, analog-to-digital converter including the delta modulator, and communication device including the delta modulator

A reference voltage circuit is provided. The reference voltage circuit includes a first current bias circuit including a first node; a second current bias circuit including a plurality of NMOS transistors and a second node, and an amplifier configured to output a reference voltage having same value as the second voltage. The plurality of NMOS transistors include a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is connected to the first node, and the plurality of NMOS transistors are connected to the second node and configured to perform a sub-threshold operation based on a first voltage of the first node so that a second voltage is generated at the second node.

Terminal device including reference voltage circuit

An analog-to-digital converter includes a sample hold circuit configured to receive an analog input signal based on an operating mode, the operating mode being one of at least two modes including a sample mode and a hold mode. The sample hold circuit includes a first transistor including a control terminal and a first terminal, the first transistor configured to receive a control signal via the control terminal and receive the analog input signal via the first terminal. The analog-to-digital converter further includes a bootstrap switch operationally connected to the control terminal and the first terminal of the first transistor, the bootstrap switch configured to form a first current path from a power source based on the analog input signal and a boosted voltage of the control terminal of the first transistor in the sample mode, the control terminal bing along the first current path in the sample mode.

Analog-to-digital converter and communication device including the same

A semiconductor device and operating method thereof are provided. The semiconductor device includes a mode controller configured to output a control signal of a first level in a first mode, and output a control signal of a second level that is different from the first level in a second mode that is different from the first mode; and a successive approximation register analog-to-digital converter (SAR ADC) configured to convert an analog input signal into a digital output signal using a plurality of variable sampling capacitors, wherein each of the plurality of variable sampling capacitors comprises a first sampling capacitor having a first capacitance, and a second sampling capacitor having a second capacitance, wherein, in the first mode, the SAR ADC is configured to receive the control signal of the first level and connect the first sampling capacitor and the second sampling capacitor to either of a first voltage and a second voltage that is different from the first voltage to convert the analog input signal into the digital output signal, and wherein, in the second mode, the SAR ADC is configured to receive the control signal of the second level and connect any one of the first sampling capacitor and the second sampling capacitor to either of the first voltage and the second voltage to convert the analog input signal into the digital output signal.

Semiconductor device comprising successive approximation register analog to digital converter with variable sampling capacitor

Provided are a semiconductor device and a System on Chip (SoC). The semiconductor device includes a reference capacitor that receives a reference voltage from a reference voltage generator, a first successive approximation register analog-to-digital converter (SAR ADC), for converting a first analog signal into a first digital signal, using a first sampling capacitor that has a first capacitance and is connected to the reference capacitor through a first switching element, and a second sampling capacitor that has a second capacitance that is less than that of the first sampling capacitor, connected to the reference capacitor through a second switching element, a second SAR ADC, for converting a second analog signal into a second digital signal, using a third sampling capacitor that has a third capacitance, connected to the reference capacitor through a third switching element, and a fourth sampling capacitor that has a fourth capacitance that is less than that of the third sampling capacitance connected to the reference capacitor through a fourth switching element, and a controller configured to connect the first switching element and the third switching element to the reference capacitor at different times.

Semiconductor device comprising analog to digital converters sharing reference capacitor and system on chip comprising the same

Provided is an apparatus for analog-digital converting that includes a Most Significant Bit (MSB)-Digital Analog Converter (DAC) for converting a digital signal into an analog signal, a trim capacitor, a Least Significant Bit (LSB)-DAC, coupled to the trim capacitor, for converting a digital signal into an analog signal, a bridge capacitor connecting the MSB-DAC and the LSB-DAC, a comparator for measuring a voltage value at the MSB-DAC and LSB-DAC and outputting a result of comparing with a sampled voltage value, and a controller for generating first measurement data by digital converting a first measurement value output from the comparator by applying a reference voltage to a unit capacitor of the MSB-DAC, for generating second measurement data by digital converting a second measurement value output from the comparator by applying the reference voltage to the LSB-DAC, and controlling the trim capacitor by comparing the first and second measurement data.

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Seoul, South Korea

Seung-hyun Oh