Samsung Electronics Co., Ltd.

Yonsei University

Seung-hyun Lim

In-Seok Yeo

Kwi-Sung Yoo

Kyong-Hee Joo

Jae-young Ahn

Min-ho Kwon

Bi-O Kim

Jin-Ho Park

Ki-Hyun Hwang

Wun-Ki Jung

Ki-hyun Hwang

Chang-Woo Sun

Jin-Tae Noh

Yu-Jin Park

Chi-Ho Hwang

Jung-Dal Choi

Jae-Hong Kim

Sang-min Lee

Dong-Hun Lee

Won-Cheol Jeong

Sun-Il Shim

Jae-Kwan Park

Seog-Heon Ham

Hyun-Suk Kim

Shuichi Shimokawa

Yong Kyun Lim

Dong-min Kim

Toshiro Nakanishi

Kyoung-Min Koh

Youngcheol Chae

Kyu-Tae Na

Chang-Seok Kang

Jun-Kyu Yang

Takafumi Usui

Woo-Seok Choi

Sun-Jung Kim

Yong-Won Cha

Eun-young Jin

Zong-liang Huo

Sang-ryol Yang

Kang-sun Lee

Jin-tae Noh

Sung-Ho Suh

Kyong-hee Joo

Beoung-ouk Min

Chang-woo Sun

Sang-hyun Cho

Woo-jin Jo

Kyojin David Choo

An analog-to-digital converter configured to convert an analog signal into a digital signal includes a first converter configured to receive an input signal of an analog type, compare the input signal with a plurality of reference signals, select one of the plurality of reference signals based on the comparison, and output an upper bit that is a portion of the digital signal based on the selected reference signal, a second converter configured to perform an oversampling operation n times based on a residue signal indicating a difference between an upper analog signal corresponding to the upper bit value and the input signal and output an intermediate bit value of the digital signal corresponding to the first to n-th oversampling signals generated respectively during the oversampling operations performed n times, and a third converter configured to output a lower bit value of the digital signal corresponding to the n-th oversampling signal.

Analog-to-digital converter and image sensor having the same

A solid-state image sensor of an electronic device includes a plurality of pixels arranged in a matrix form and having a plurality of phase difference pixel of the plurality of pixels. The plurality of phase difference pixels are arranged at locations of pixels that are commonly read out in a plurality of different skip readout modes.

Solid-state image sensor, electronic device, and auto focusing method

An image sensor is provided. The image sensor includes a converter configured to convert a photoelectric converted analog signal in a unit pixel into a digital signal including a plurality of bits, a data transfer unit configured to selectively output the converted digital signal output from the converter in units of bits in response to a control signal, and including a plurality of switching circuits which are serially connected; and a memory configured to store data output from the data transfer unit.

Device and method of transferring sensed data in image sensor

A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.

Semiconductor device and method of manufacturing the same

An image sensor includes a pixel array and a plurality of pairs of column lines. The pixel array includes a plurality of unit pixel areas arranged in a plurality of rows and columns. Each of the unit pixel areas includes a readout circuit connected to a corresponding pair of column lines, and first and second photo-electric conversion devices sharing the readout circuit. Each of the unit pixel areas is configured to output a first pixel signal corresponding to a photoelectron generated by the first photo-electric conversion device through the first column line, and to output a second pixel signal corresponding to a photoelectron generated by the second photo-electric conversion device through the second column line.

Unit pixels configured to output different pixel signals through different lines and image sensors including the same

Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.

Vertical memory devices and methods of manufacturing the same

An analog to digital converter (ADC) can include a multi-input comparison unit configured to compare a pixel voltage from an image sensor, a comparison voltage comprising a stepped voltage modified during a coarse mode of operation, and a ramp voltage comprising a ramped voltage modified to one another during a fine mode of operation, to provide a comparison result signal that indicates whether the comparison voltage combined with the ramp voltage is greater than or less than the pixel voltage. A selection control signal generation unit can receive the comparison result signal and a mode control signal, to indicate the coarse or fine mode, to provide a selection control signal allowing modification of the comparison voltage in the coarse mode and to hold the comparison voltage constant in the fine mode. A reference voltage selection unit can receive the selection control signal to control modification of the comparison voltage.

Analog to digital converters, image sensor systems, and methods of operating the same

An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.

Offset canceling circuit, sampling circuit and image sensor

An analog-to-digital converter includes a comparison signal generation unit and a control unit. The comparison signal generation unit determines a logic level of a comparison signal by comparing an input signal with a selected reference signal based on a switch control signal in a first comparison mode, and by comparing a difference voltage with a ramp signal based on the switch control signal in a second comparison mode. The difference voltage is generated based on the input signal and the selected reference signal such that a level of the difference voltage is lower than a fine voltage level corresponding to a voltage level of the selected reference signal in the second comparison mode. The control unit generates the switch control signal based on the comparison signal and a mode selection signal.

Analog-to-digital converter having a comparison signal generation unit and image sensor including the same

Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

Non-volatile memory devices

The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.

Charge trap flash memory device and memory card and system including the same

Non-volatile memory devices can be fabricated by forming a tunnel dielectric layer on a semiconductor substrate, subjecting the semiconductor substrate having the tunnel dielectric layer to an atomic layer deposition (ALD) process to form nanocrystals on the tunnel dielectric layer, removing the semiconductor substrate having the nanocrystals from an atomic layer deposition chamber, forming a control gate dielectric layer on the semiconductor substrate having the nanocrystal, and forming a control gate electrode on the semiconductor substrate having the control gate dielectric layer.

Methods of fabricating non-volatile memory devices including nanocrystals

In a method of forming a thin layer having a desired composition, a source gas is provided onto a substrate loaded in a chamber for a first time, and the source gas is chemisorbed onto the substrate. While the source gas is provided, a plasma is generated in the chamber for a second time to change the chemisorbed source gas into the thin layer having the desired composition. The thin layer may have a stoichiometrical composition or a non-stoichiometrical composition.

Method of forming a thin layer and method of manufacturing a non-volatile semiconductor device using the same

In a method of forming a silicon-rich nanocrystalline structure by an ALD process, a first gas including a first silicon compound is provided onto an object to form a silicon-rich chemisorption layer on the object. A second gas including oxygen is provided onto the silicon-rich chemisorption layer to form a silicon-rich insulation layer on the object. A third gas including a second silicon compound is provided onto the silicon-rich insulation layer to form a silicon nanocrystalline layer on the silicon-rich insulation layer. The first gas, the second gas and the third gas may be repeatedly provided to alternately form the silicon-rich nanocrystalline structure having a plurality of silicon-rich insulation layers and a plurality of silicon nanocrystalline layers on the object.

Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same

Growing community of inventors

Yongin-si, South Korea

Seung-hyun Lim