Samsung Electronics Co., Ltd.

Seung Hyun Lim

Jae Hong Kim

Seog Heon Ham

Dae Hwa Paik

Kwi Sung Yoo

Min Ho Kwon

Dong Hun Lee

Hanmei Choi

Kyoung Min Koh

Haesick Sul

Hyosang Kim

Minji Hwang

Young Woo Park

Woo Sung Lee

Jae Duk Lee

Ji Yong Park

Sang Hyun Cho

Dong Seog Eun

Yu Jin Park

Jong Won Kim

Chang Seok Kang

Han Kook Cho

Sin Hwan Lim

Jae Woo Lim

Dae Hoon Bae

Jin Ho Seo

Gun Hee Han

Jinwoo Kim

Jaehong Kim

Jae Ho Choi

Jae Young Park

Han Vit Yang

Bio Kim

Yong Kyun Lim

Seong Hoon Jeong

Wun-Ki Jung

Jae Young Ahn

Jeong Heum Lee

Jae Cheol Yun

Jeon Il Lee

Jae Jin Jung

Young Jin Noh

Sung Ho Suh

Sanghyun Cho

Hong Bum Park

Daehwa Paik

Kwang Min Park

Dong Chul Yoo

Keunyung Byun

Soon Hwa Kang

Kun Hee Cho

Jin Uk Jeon

An image sensor includes a first column line and a second column line configured to extend in a first direction, a plurality of pixel groups configured to connect to the first column line or the second column line and to comprise a plurality of pixels in each of the plurality of pixel groups, a bias circuit configured to comprise a first current circuit and a second current circuit configured to output different bias currents in a first operational mode, and a switching circuit configured to connect the first column line to the first current circuit and connect the second column line to the second current circuit during a first time period, and to connect the first column line to the second current circuit and connect the second column line to the first current circuit during a second time period subsequent to the first time period in the first operational mode.

Image sensor

Disclosed is an image sensor. The image sensor includes an active pixel sensor array including first to fourth pixel units sequentially arranged in a column direction, and each of the first to fourth pixel units is composed of a plurality of pixels. A first pixel group including the first and second pixel units is connected to a first column line, and a second pixel group including the third pixel unit and the fourth pixel unit is connected to a second column line. The image sensor includes a correlated double sampling circuit including first and second correlated double samplers and configured to convert a first sense voltage sensed from a selected pixel of the first pixel group and a second sense voltage sensed from a selected pixel of the second pixel group into a first correlated double sampling signal and a second correlated double sampling signal, respectively.

Image sensor supporting various operating modes and operating method thereof

An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.

Image sensor chip that feeds back voltage and temperature information, and an image processing system having the same

Disclosed is an image sensor that includes a pixel array including first pixels sharing a first floating diffusion region and second pixels sharing a second floating diffusion region, a first analog-to-digital converter, a second analog-to-digital converter, and a switch circuit. In a first mode, the first analog-to-digital converter processes the first pixels, and the second analog-to-digital converter processes the second pixels. In the second mode, the first analog-to-digital converter processes a first image component of a pixel signal of the first pixels, and the second analog-to-digital converter processes a second image component of the pixel signal of the first pixels. An HDR image is implemented based on processing results of the first analog-to-digital converter and the second analog-to-digital converter.

Image sensor for implementing high dynamic range image using dual conversion gain

An image sensor and an image processing system including the same are provided. The image sensor includes a pixel array including a plurality of pixels each connected to one of first through m-th column lines to output a pixel signal, where 'm' is an integer of at least 2; analog-to-digital converters each configured to receive the pixel signal corresponding to one of the first through m-th column lines, to compare the pixel signal with a ramp signal, and to convert the pixel signal to a digital pixel signal; and a blocking circuit connected to an input terminal of at least one of the analog-to-digital converters to block an influence of an operation of others among the analog-to-digital converters.

Image sensor for improving linearity of analog-to-digital converter and image processing system including the same

A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Vertical memory devices having dummy channel regions

A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.

Semiconductor devices including gate dielectric structures

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Hwaseong-si, South Korea

Seung Hyun Lim