Western Digital Technologies, Inc.

Anaflash Inc.

Semibrain Inc.

Seung-Hwan Song

Zvonimir Z Bandic

Robert Eugeniu Mateescu

Minghai Qin

Viacheslav Anatolyevich Dubeyko

Sang-Soo Lee

Yongjune Kim

Kiran Kumar Gunnam

Pankaj Mehra

Chao Sun

Arup De

Brian Walter O'Krafka

Dejan Vucinic

Vidyabhushan Mohan

Daewung Kim

Younghee Jeon

Ji Hye Hur

Sihwan Kim

The present invention discloses a hardware computing device comprising a non-transitory computer-readable storage medium configured to store one or more computer-executable instructions; a host processing unit configured to determine whether and how artificial neural network model-based computations should be assigned to a second processing unit; and a hardware accelerator configured to execute one or more artificial neural network computations assigned by the host processing unit, wherein the hardware accelerator sequentially executes instructions in an instruction stream with a single instruction fetch by detecting a successive address of a next instruction.

Flash based transformer accelerator

An analog multiplier accumulator array comprises analog multipliers organized in a matrix of rows and columns, each of the multiplier comprising one or more than one analog input signal line coupled to the analog multipliers in a row of the array; an analog level sensing circuit; a set of bit lines, each bit line electrically connected to the analog multiplier in each column of the row; and an analog accumulator configured to connect the set of the bit lines to an analog level sensing circuit for generating digital output signals, wherein an access transistor connected to the analog input line and a variable resistor form the analog multiplier.

Multiply-accumulate unit

A neural network unit is disclosed. This neural network unit includes: a main synapse array having a plurality of main synapses in rows and columns of the array, each connected to one or more bit lines associated with the network unit; a main synapse driver for applying an input to one or more of the main synapses in a row; a reference synapse for generating a particular output to a selected one or more associated bit lines; and, a sensing circuit for controlling the reference synapse in generating the output in a selected column of the array, wherein the sensing circuit is adapted to infer an output from one or more main synapses in a selected column by: defining a reference range of the output to be generated by reference synapse; setting a reference level from the reference range; activating a selected reference synapse to implement the reference level that is set or adjusted; and comparing an output from the main synapse summed with the output from the activated reference synapse in the selected column with a threshold value predetermined.

Neural network unit

A serialized neural network computing unit is disclosed. This computing unit comprises: a bit line; a memory array having a plurality of memory blocks, each memory block have one or more than one memory cells, each cell connected to the bit line; a control circuit configured to: apply a serialized input to the memory cells in a sequence such that outputs of the memory cells are produced in a sequence in response to the serialized input, wherein each of the outputs corresponds to a multiplication of the input and a weight value stored in the memory cell; and set a group of reference current levels, each having a specific current amount, for the control circuit to control the memory cells in generating respective output currents corresponding to the set of reference current levels.

Serialized neural network computing unit

A driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including: a first circuit for supplying the memory cell with a first read reference voltage through the output node; a second circuit for supplying the memory cell with a second read reference voltage through the output node; and a third circuit for controlling an operation of the second circuit, wherein a range of the second read reference voltage at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell.

Memory cell driver circuit

A selective non-volatile memory programming method for a selected memory cell in a memory array is described so as to reduce or avoid program disturbance on an unselected memory cell. This selective programming method comprises: applying a programming pulse to a selected memory cell to be programmed and an unselected memory cell, wherein the programming pulse allows a change of the unselected memory cell within a range specified; boosting a region of the unselected memory cell; and setting a threshold time of the programming pulse, wherein the threshold time is defined when an absolute magnitude of a voltage difference between a floating gate of the unselected memory cell and the boosted region of the unselected memory cell reaches a threshold value defined.

Logic compatible flash memory programming with a pulse width control scheme

A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: a first input signal line for providing a first input signal; a reference signal line for providing a reference signal; first and second output lines for carrying first and second output signals therethrough, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: a first upper select transistor having a gate that is electrically coupled to the first input signal line; and a first resistive changing element having one end connected to the first select transistor in series and another end electrically coupled to the reference signal line. The value of the first resistive changing element may be programmable to change the magnitude of an output signal. The drain of the first upper select transistor of the first cell is electrically coupled to the first output line and the drain of the first upper select transistor of the second cell is electrically coupled to the second output line.

Neural network circuits having non-volatile synapse arrays

A non-volatile memory combines a data cell and a reference cell. The data cell includes a coupling structure and a transistor stack. The transistor stack is electrically coupled to the coupling structure. The data cell can store data and output a data signal that corresponds to the data. The reference cell includes a transistor stack that has the same structure as that of the data cell and outputs a reference signal. A column circuit is electrically coupled to the data cell and the first reference cell and configured to process the data signal using the reference signal.

Logic compatible embedded flash memory

A non-volatile synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; first and second output lines, and first and second cells for generating the first and second output signals, respectively. Each of the first and second cells includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor of the first cell is electrically coupled to the first output line and the drain of the upper select transistor of the second cell is electrically coupled to the second output line.

A synapse circuit of a non-volatile neural network. The synapse includes: an input signal line; a reference signal line; an output line, and a cell for generating the output signal. The cell includes: an upper select transistor having a gate that is electrically coupled to the input signal line; and a resistive changing element having one end connected to the upper select transistor in series and another end electrically coupled to the reference signal line. The value of the resistive changing element is programmable to change the magnitude of an output signal. The drain of the upper select transistor is electrically coupled to the first output line.

A host compiles code to perform a set of one or more database operations on target and embeds an indication of whether the target data is randomly accessed data or sequentially accessed data. The compiled code is transmitted to the compute engine inside a memory system that maintains a first portion of memory for storing sequentially accessed data and a second portion of memory for storing randomly accessed data. The memory system (e.g. SSD) maintains reduced size L2P tables in volatile working memory by maintaining coarse L2P tables in the working memory for use with sequentially accessed data and maintaining fine L2P tables in the working memory for use with randomly accessed data. The compute engine uses the compiled code to perform the set of one or more database operations on the target data using the working memory.

Hybrid logical to physical address translation for non-volatile storage devices with integrated compute module

A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.

Data reliability information in a non-volatile memory device

A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.

Non-volatile storage system with compute engine to accelerate big data applications

A non-volatile storage system is configured to reclaim bad blocks. One embodiment includes determining that a block of non-volatile memory cells is a bad block, leaving the block idle for a period of time to allow for self-curing of the block, verifying success of the self-curing, refreshing the block, verifying that the refresh was successful and subsequently using the block to store host data.

Non-volatile storage system that reclaims bad blocks

NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.

Growing community of inventors

San Jose, CA, United States of America

Seung-Hwan Song